Get vdd/gnd from properties if it is defined.

compiler/base/hierarchy_design.py

@@ -40,8 +40,6 @@ class hierarchy_design(hierarchy_spice.spice, hierarchy_layout.layout):
         self.drc_errors = "skipped"
         self.lvs_errors = "skipped"
 
-        self.name = name
-        self.cell_name = cell_name
         hierarchy_spice.spice.__init__(self, name, cell_name)
         hierarchy_layout.layout.__init__(self, name, cell_name)
         self.init_graph_params()

compiler/base/hierarchy_layout.py

@@ -32,8 +32,10 @@ class layout():
     """
 
     def __init__(self, name, cell_name):
+        # This gets set in both spice and layout so either can be called first.
         self.name = name
         self.cell_name = cell_name
+        
         self.width = None
         self.height = None
         self.bounding_box = None
@@ -43,6 +45,7 @@ class layout():
         self.pin_map = {}    # Holds name->pin_layout map for all pins
         self.visited = []    # List of modules we have already visited
         self.is_library_cell = False # Flag for library cells
+        
         self.gds_read()
 
         try:

compiler/base/hierarchy_spice.py

@@ -28,6 +28,7 @@ class spice():
     """
 
     def __init__(self, name, cell_name):
+        # This gets set in both spice and layout so either can be called first.
         self.name = name
         self.cell_name = cell_name
 
@@ -78,7 +79,6 @@ class spice():
         """ Adds a pin_list to the pins list """
         # The type list can be a single type for all pins
         # or a list that is the same length as the pin list.
-            
         if type(pin_type)==str:
             for pin in pin_list:
                 debug.check(pin_type in self.valid_signal_types,

compiler/bitcells/bitcell_base.py

@@ -26,6 +26,9 @@ class bitcell_base(design.design):
             self.nets_match = self.do_nets_exist(prop.storage_nets)
             self.mirror = prop.mirror
             self.end_caps = prop.end_caps
+            self.supplies = [prop.pin.vdd, prop.pin.gnd]
+        else:
+            self.supplies = ["vdd", "gnd"]
         
     def get_stage_effort(self, load):
         parasitic_delay = 1

compiler/modules/bitcell_base_array.py

@@ -35,10 +35,10 @@ class bitcell_base_array(design.design):
         self.rbl_wordline_names = [[] for port in self.all_ports]
         self.all_rbl_wordline_names = []
 
-        # The supply pin namesn
+        # The supply pin names
-        self.bitcell_supplies = ["vdd", "gnd"]
+        self.bitcell_supplies = self.cell.supplies
         # If the technology needs renaming of the supplies
-        self.supplies = self.bitcell_supplies
+        self.supplies = ["vdd", "gnd"]
 
     def create_all_bitline_names(self):
         for col in range(self.column_size):