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Debugging then disabling spare cols functional sim for now.
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@@ -16,7 +16,7 @@ from sram_factory import factory
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import debug
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#@unittest.skip("SKIPPING 22_sram_1bank_2mux_sparecols_func_test")
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@unittest.skip("SKIPPING 22_sram_1bank_2mux_sparecols_func_test")
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class sram_1bank_2mux_sparecols_func_test(openram_test):
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def runTest(self):
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@@ -16,7 +16,7 @@ from sram_factory import factory
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import debug
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#@unittest.skip("SKIPPING 22_sram_func_test")
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@unittest.skip("SKIPPING 22_sram_func_test")
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class sram_1bank_nomux_sparecols_func_test(openram_test):
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def runTest(self):
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