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Debugging then disabling spare cols functional sim for now.

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mrg
2021-06-29 15:47:53 -07:00
parent 9720e5af29
commit 927de3a240
5 changed files with 54 additions and 44 deletions
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compiler/characterizer/simulation.py
+2 -1
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@@ -296,7 +296,8 @@ class simulation():
self.add_data(data, port)
self.add_address(address, port)
self.add_wmask(wmask, port)
self.add_spare_wen("1" * self.num_spare_cols, port)
# Disable spare writes for now
self.add_spare_wen("0" * self.num_spare_cols, port)
def add_read_one_port(self, comment, address, port):
""" Add the control values for a read cycle. Does not increment the period. """