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Bitcell supply routing fixes.

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Flatten and simplify 1rw 1r bitcell.
Move bitcell vias to M3 if rotation is limited.
Simplify replica bitcell vdd routing.
This commit is contained in:
Matt Guthaus
2018-11-30 12:32:13 -08:00
parent 7e054a51e2
commit 90d1fa7c43
6 changed files with 36 additions and 33 deletions
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compiler/modules/bitcell_array.py
+2 -1
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@@ -138,7 +138,8 @@ class bitcell_array(design.design):
inst = self.cell_inst[row,col]
for pin_name in ["vdd", "gnd"]:
for pin in inst.get_pins(pin_name):
self.add_power_pin(pin_name, pin.center(), 0, pin.layer=="metal1")
self.add_power_pin(pin_name, pin.center(), 0, pin.layer)
def analytical_delay(self, slew, load=0):
from tech import drc