mirror of https://github.com/VLSIDA/OpenRAM.git
Actually changed the noops default data in this commit.
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parent
53fa6108e1
commit
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@ -764,7 +764,7 @@ class delay():
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self.add_address(address, port)
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self.add_address(address, port)
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#This value is hard coded here. May want to make it a member variable or input to give control over this value
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#This value is hard coded here. Possibly change to member variable or set in add_noop_one_port
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noop_data = "0"*self.word_size
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noop_data = "0"*self.word_size
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#Add noops to all other ports.
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#Add noops to all other ports.
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for unselected_port in self.readwrite_ports+self.read_ports+self.write_ports:
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for unselected_port in self.readwrite_ports+self.read_ports+self.write_ports:
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@ -791,10 +791,12 @@ class delay():
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self.add_data(data,port)
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self.add_data(data,port)
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self.add_address(address,port)
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self.add_address(address,port)
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#This value is hard coded here. Possibly change to member variable or set in add_noop_one_port
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noop_data = "0"*self.word_size
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#Add noops to all other ports.
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#Add noops to all other ports.
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for readwrite_port in self.readwrite_ports+self.read_ports+self.write_ports:
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for readwrite_port in self.readwrite_ports+self.read_ports+self.write_ports:
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if readwrite_port != port:
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if readwrite_port != port:
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self.add_noop_one_port(address, data, readwrite_port)
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self.add_noop_one_port(address, noop_data, readwrite_port)
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def gen_test_cycles_one_port(self, read_port, write_port):
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def gen_test_cycles_one_port(self, read_port, write_port):
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"""Intended but not implemented: Returns a list of key time-points [ns] of the waveform (each rising edge)
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"""Intended but not implemented: Returns a list of key time-points [ns] of the waveform (each rising edge)
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