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commiting changes from most recent pull from dev

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Michael Timothy Grimes
2018-05-22 17:30:51 -07:00
parent 17769f27c6 f34c4eb7dc
commit 8f131ddb2f
178 changed files with 802 additions and 42105 deletions
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compiler/modules/bank.py
+6 -8
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@@ -26,6 +26,7 @@ class bank(design.design):
"bitcell_array", "sense_amp_array", "precharge_array",
"column_mux_array", "write_driver_array", "tri_gate_array",
"bank_select"]
from importlib import reload
for mod_name in mod_list:
config_mod_name = getattr(OPTS, mod_name)
class_file = reload(__import__(config_mod_name))
@@ -130,8 +131,8 @@ class bank(design.design):
def compute_sizes(self):
""" Computes the required sizes to create the bank """
self.num_cols = self.words_per_row*self.word_size
self.num_rows = self.num_words / self.words_per_row
self.num_cols = int(self.words_per_row*self.word_size)
self.num_rows = int(self.num_words / self.words_per_row)
self.row_addr_size = int(log(self.num_rows, 2))
self.col_addr_size = int(log(self.words_per_row, 2))
@@ -320,7 +321,7 @@ class bank(design.design):
y_offset = self.sense_amp_array.height+self.column_mux_height \
+ self.write_driver_array.height + self.m2_gap + self.tri_gate_array.height
self.tri_gate_array_inst=self.add_inst(name="tri_gate_array",
mod=self.tri_gate_array,
mod=self.tri_gate_array,
offset=vector(0,y_offset).scale(-1,-1))
temp = []
@@ -852,9 +853,7 @@ class bank(design.design):
def analytical_delay(self, slew, load):
""" return analytical delay of the bank"""
msf_addr_delay = self.msf_address.analytical_delay(slew, self.row_decoder.input_load())
decoder_delay = self.row_decoder.analytical_delay(msf_addr_delay.slew, self.wordline_driver.input_load())
decoder_delay = self.row_decoder.analytical_delay(slew, self.wordline_driver.input_load())
word_driver_delay = self.wordline_driver.analytical_delay(decoder_delay.slew, self.bitcell_array.input_load())
@@ -866,7 +865,6 @@ class bank(design.design):
data_t_DATA_delay = self.tri_gate_array.analytical_delay(bl_t_data_out_delay.slew, load)
result = msf_addr_delay + decoder_delay + word_driver_delay \
+ bitcell_array_delay + bl_t_data_out_delay + data_t_DATA_delay
result = decoder_delay + word_driver_delay + bitcell_array_delay + bl_t_data_out_delay + data_t_DATA_delay
return result
compiler/modules/control_logic.py
+1
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@@ -70,6 +70,7 @@ class control_logic(design.design):
self.inv8 = pinv(size=16, height=dff_height)
self.add_mod(self.inv8)
from importlib import reload
c = reload(__import__(OPTS.replica_bitline))
replica_bitline = getattr(c, OPTS.replica_bitline)
# FIXME: These should be tuned according to the size!
compiler/modules/delay_chain.py
+1
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@@ -28,6 +28,7 @@ class delay_chain(design.design):
self.num_inverters = 1 + sum(fanout_list)
self.num_top_half = round(self.num_inverters / 2.0)
from importlib import reload
c = reload(__import__(OPTS.bitcell))
self.mod_bitcell = getattr(c, OPTS.bitcell)
self.bitcell = self.mod_bitcell()
compiler/modules/dff_array.py
+1
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@@ -20,6 +20,7 @@ class dff_array(design.design):
design.design.__init__(self, name)
debug.info(1, "Creating {}".format(self.name))
from importlib import reload
c = reload(__import__(OPTS.dff))
self.mod_dff = getattr(c, OPTS.dff)
self.dff = self.mod_dff("dff")
compiler/modules/dff_buf.py
+1
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@@ -20,6 +20,7 @@ class dff_buf(design.design):
design.design.__init__(self, name)
debug.info(1, "Creating {}".format(self.name))
from importlib import reload
c = reload(__import__(OPTS.dff))
self.mod_dff = getattr(c, OPTS.dff)
self.dff = self.mod_dff("dff")
compiler/modules/dff_inv.py
+1
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@@ -19,6 +19,7 @@ class dff_inv(design.design):
design.design.__init__(self, name)
debug.info(1, "Creating {}".format(self.name))
from importlib import reload
c = reload(__import__(OPTS.dff))
self.mod_dff = getattr(c, OPTS.dff)
self.dff = self.mod_dff("dff")
compiler/modules/hierarchical_decoder.py
+1
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@@ -21,6 +21,7 @@ class hierarchical_decoder(design.design):
def __init__(self, rows):
design.design.__init__(self, "hierarchical_decoder_{0}rows".format(rows))
from importlib import reload
c = reload(__import__(OPTS.bitcell))
self.mod_bitcell = getattr(c, OPTS.bitcell)
self.bitcell_height = self.mod_bitcell.height
compiler/modules/hierarchical_predecode.py
+1
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@@ -19,6 +19,7 @@ class hierarchical_predecode(design.design):
self.number_of_outputs = int(math.pow(2, self.number_of_inputs))
design.design.__init__(self, name="pre{0}x{1}".format(self.number_of_inputs,self.number_of_outputs))
from importlib import reload
c = reload(__import__(OPTS.bitcell))
self.mod_bitcell = getattr(c, OPTS.bitcell)
compiler/modules/ms_flop_array.py
+9 -5
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@@ -20,6 +20,7 @@ class ms_flop_array(design.design):
design.design.__init__(self, name)
debug.info(1, "Creating {}".format(self.name))
from importlib import reload
c = reload(__import__(OPTS.ms_flop))
self.mod_ms_flop = getattr(c, OPTS.ms_flop)
self.ms = self.mod_ms_flop("ms_flop")
@@ -27,7 +28,7 @@ class ms_flop_array(design.design):
self.width = self.columns * self.ms.width
self.height = self.ms.height
self.words_per_row = self.columns / self.word_size
self.words_per_row = int(self.columns / self.word_size)
self.create_layout()
@@ -57,13 +58,16 @@ class ms_flop_array(design.design):
else:
base = vector((i+1)*self.ms.width,0)
mirror = "MY"
self.ms_inst[i/self.words_per_row]=self.add_inst(name=name,
index = int(i/self.words_per_row)
self.ms_inst[index]=self.add_inst(name=name,
mod=self.ms,
offset=base,
mirror=mirror)
self.connect_inst(["din[{0}]".format(i/self.words_per_row),
"dout[{0}]".format(i/self.words_per_row),
"dout_bar[{0}]".format(i/self.words_per_row),
self.connect_inst(["din[{0}]".format(index),
"dout[{0}]".format(index),
"dout_bar[{0}]".format(index),
"clk",
"vdd", "gnd"])
compiler/modules/replica_bitline.py
+2 -2
View File
@@ -18,6 +18,7 @@ class replica_bitline(design.design):
def __init__(self, delay_stages, delay_fanout, bitcell_loads, name="replica_bitline"):
design.design.__init__(self, name)
from importlib import reload
g = reload(__import__(OPTS.delay_chain))
self.mod_delay_chain = getattr(g, OPTS.delay_chain)
@@ -132,11 +133,10 @@ class replica_bitline(design.design):
""" Connect all the signals together """
self.route_vdd()
self.route_gnd()
self.route_vdd_gnd()
self.route_access_tx()
def route_vdd_gnd(self):
""" Route all the vdd and gnd pins to the top level """
def route_vdd_gnd(self):
""" Propagate all vdd/gnd pins up to this level for all modules """
# These are the instances that every bank has
compiler/modules/sense_amp_array.py
+9 -6
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@@ -14,6 +14,7 @@ class sense_amp_array(design.design):
design.design.__init__(self, "sense_amp_array")
debug.info(1, "Creating {0}".format(self.name))
from importlib import reload
c = reload(__import__(OPTS.sense_amp))
self.mod_sense_amp = getattr(c, OPTS.sense_amp)
self.amp = self.mod_sense_amp("sense_amp")
@@ -33,7 +34,8 @@ class sense_amp_array(design.design):
def add_pins(self):
for i in range(0,self.row_size,self.words_per_row):
self.add_pin("data[{0}]".format(i/self.words_per_row))
index = int(i/self.words_per_row)
self.add_pin("data[{0}]".format(index))
self.add_pin("bl[{0}]".format(i))
self.add_pin("br[{0}]".format(i))
@@ -62,12 +64,14 @@ class sense_amp_array(design.design):
br_offset = amp_position + br_pin.ll().scale(1,0)
dout_offset = amp_position + dout_pin.ll()
index = int(i/self.words_per_row)
inst = self.add_inst(name=name,
mod=self.amp,
offset=amp_position)
self.connect_inst(["bl[{0}]".format(i),
"br[{0}]".format(i),
"data[{0}]".format(i/self.words_per_row),
"data[{0}]".format(index),
"en", "vdd", "gnd"])
@@ -85,19 +89,18 @@ class sense_amp_array(design.design):
layer="metal3",
offset=vdd_pos)
self.add_layout_pin(text="bl[{0}]".format(i/self.words_per_row),
self.add_layout_pin(text="bl[{0}]".format(i),
layer="metal2",
offset=bl_offset,
width=bl_pin.width(),
height=bl_pin.height())
self.add_layout_pin(text="br[{0}]".format(i/self.words_per_row),
self.add_layout_pin(text="br[{0}]".format(i),
layer="metal2",
offset=br_offset,
width=br_pin.width(),
height=br_pin.height())
self.add_layout_pin(text="data[{0}]".format(i/self.words_per_row),
self.add_layout_pin(text="data[{0}]".format(index),
layer="metal2",
offset=dout_offset,
width=dout_pin.width(),
compiler/modules/single_level_column_mux_array.py
+1 -1
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@@ -19,7 +19,7 @@ class single_level_column_mux_array(design.design):
debug.info(1, "Creating {0}".format(self.name))
self.columns = columns
self.word_size = word_size
self.words_per_row = self.columns / self.word_size
self.words_per_row = int(self.columns / self.word_size)
self.add_pins()
self.create_layout()
self.DRC_LVS()
compiler/modules/tri_gate_array.py
+8 -5
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@@ -14,6 +14,7 @@ class tri_gate_array(design.design):
design.design.__init__(self, "tri_gate_array")
debug.info(1, "Creating {0}".format(self.name))
from importlib import reload
c = reload(__import__(OPTS.tri_gate))
self.mod_tri_gate = getattr(c, OPTS.tri_gate)
self.tri = self.mod_tri_gate("tri_gate")
@@ -22,7 +23,7 @@ class tri_gate_array(design.design):
self.columns = columns
self.word_size = word_size
self.words_per_row = self.columns / self.word_size
self.words_per_row = int(self.columns / self.word_size)
self.width = (self.columns / self.words_per_row) * self.tri.width
self.height = self.tri.height
@@ -53,24 +54,26 @@ class tri_gate_array(design.design):
self.tri_inst[i]=self.add_inst(name=name,
mod=self.tri,
offset=base)
self.connect_inst(["in[{0}]".format(i/self.words_per_row),
"out[{0}]".format(i/self.words_per_row),
index = int(i/self.words_per_row)
self.connect_inst(["in[{0}]".format(index),
"out[{0}]".format(index),
"en", "en_bar", "vdd", "gnd"])
def add_layout_pins(self):
for i in range(0,self.columns,self.words_per_row):
index = int(i/self.words_per_row)
in_pin = self.tri_inst[i].get_pin("in")
self.add_layout_pin(text="in[{0}]".format(i/self.words_per_row),
self.add_layout_pin(text="in[{0}]".format(index),
layer="metal2",
offset=in_pin.ll(),
width=in_pin.width(),
height=in_pin.height())
out_pin = self.tri_inst[i].get_pin("out")
self.add_layout_pin(text="out[{0}]".format(i/self.words_per_row),
self.add_layout_pin(text="out[{0}]".format(index),
layer="metal2",
offset=out_pin.ll(),
width=out_pin.width(),
compiler/modules/write_driver_array.py
+9 -7
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@@ -15,6 +15,7 @@ class write_driver_array(design.design):
design.design.__init__(self, "write_driver_array")
debug.info(1, "Creating {0}".format(self.name))
from importlib import reload
c = reload(__import__(OPTS.write_driver))
self.mod_write_driver = getattr(c, OPTS.write_driver)
self.driver = self.mod_write_driver("write_driver")
@@ -22,7 +23,7 @@ class write_driver_array(design.design):
self.columns = columns
self.word_size = word_size
self.words_per_row = columns / word_size
self.words_per_row = int(columns / word_size)
self.width = self.columns * self.driver.width
self.height = self.height = self.driver.height
@@ -51,13 +52,14 @@ class write_driver_array(design.design):
name = "Xwrite_driver{}".format(i)
base = vector(i * self.driver.width,0)
self.driver_insts[i/self.words_per_row]=self.add_inst(name=name,
mod=self.driver,
offset=base)
index = int(i/self.words_per_row)
self.driver_insts[index]=self.add_inst(name=name,
mod=self.driver,
offset=base)
self.connect_inst(["data[{0}]".format(i/self.words_per_row),
"bl[{0}]".format(i/self.words_per_row),
"br[{0}]".format(i/self.words_per_row),
self.connect_inst(["data[{0}]".format(index),
"bl[{0}]".format(index),
"br[{0}]".format(index),
"en", "vdd", "gnd"])