Added unit test for multibank

compiler/tests/27_verilog_multibank_test.py

@@ -0,0 +1,54 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys, os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+import debug
+
+
+class multibank_verilog_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+        OPTS.route_supplies=False
+        OPTS.check_lvsdrc=False
+        OPTS.netlist_only=True
+        from sram import sram
+        from sram_config import sram_config
+        c = sram_config(word_size=2,
+                        num_words=16,
+                        num_banks=2)
+        c.words_per_row=1
+        c.recompute_sizes()
+        debug.info(1, "Testing Verilog for sample 2 bit, 16 words SRAM with 2 bank")
+        # This doesn't have to use the factory since worst case
+        # it will just replaece the top-level module of the same name
+        s = sram(c, "sram_2_16_2_{0}".format(OPTS.tech_name))
+
+        vfile = s.name + ".v"
+        vname = OPTS.openram_temp + vfile
+        s.verilog_write(vname)
+
+
+        # let's diff the result with a golden model
+        golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)), vfile)
+        self.assertTrue(self.isdiff(vname, golden))
+
+        globals.end_openram()
+
+# run the test from the command line
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/Makefile

@@ -72,6 +72,7 @@ BROKEN_STAMPS = \
 	sky130/23_lib_sram_prune_test.ok \
 	sky131/23_lib_sram_test.ok \
 	%/26_hspice_pex_pinv_test.ok \
+	%/27_verilog_multibank_test.ok \
 	%/50_riscv_1k_1rw1r_func_test.ok \
 	%/50_riscv_1k_1rw_func_test.ok \
 	%/50_riscv_1rw1r_func_test.ok \

compiler/tests/golden/sram_2_16_2_scn4m_subm.v

@@ -0,0 +1,105 @@
+
+module sram  (
+`ifdef USE_POWER_PINS
+    vdd,
+    gnd,
+`endif
+    clk0,
+    addr0,
+    din0,
+    csb0,
+    web0,
+    dout0
+  );
+
+  parameter DATA_WIDTH = 2;
+  parameter ADDR_WIDTH= 4;
+
+  parameter BANK_SEL = 1;
+  parameter NUM_WMASK = 1;
+
+`ifdef USE_POWER_PINS
+  inout vdd;
+  inout gnd;
+`endif
+  input clk0;
+  input [ADDR_WIDTH - 1 : 0] addr0;
+  input [DATA_WIDTH - 1: 0] din0;
+  input csb0;
+  input web0;
+  output reg [DATA_WIDTH - 1 : 0] dout0;
+
+  reg [ADDR_WIDTH - 1 : 0] addr0_reg;
+
+  wire [DATA_WIDTH - 1 : 0] dout0_bank0;
+
+  reg web0_bank0;
+
+  reg csb0_bank0;
+
+  wire [DATA_WIDTH - 1 : 0] dout0_bank1;
+
+  reg web0_bank1;
+
+  reg csb0_bank1;
+
+
+  sram_1bank bank0 (
+`ifdef USE_POWER_PINS
+    .vdd(vdd),
+    .gnd(gnd),
+`endif
+    .clk0(clk0),
+    .addr0(addr0[ADDR_WIDTH - BANK_SEL - 1 : 0]),
+    .din0(din0),
+    .csb0(csb0_bank0),
+    .web0(web0_bank0),
+    .dout0(dout0_bank0)
+  );
+  sram_1bank bank1 (
+`ifdef USE_POWER_PINS
+    .vdd(vdd),
+    .gnd(gnd),
+`endif
+    .clk0(clk0),
+    .addr0(addr0[ADDR_WIDTH - BANK_SEL - 1 : 0]),
+    .din0(din0),
+    .csb0(csb0_bank1),
+    .web0(web0_bank1),
+    .dout0(dout0_bank1)
+  );
+
+  always @(posedge clk0) begin
+    addr0_reg <= addr0;
+  end
+
+  always @(*) begin
+    case (addr0_reg[ADDR_WIDTH - 1 : ADDR_WIDTH - BANK_SEL])
+      0: begin
+        dout0 = dout0_bank0;
+      end
+      1: begin
+        dout0 = dout0_bank1;
+      end
+    endcase
+  end
+
+  always @(*) begin
+    csb0_bank0 = 1'b1;
+    web0_bank0 = 1'b1;
+    csb0_bank1 = 1'b1;
+    web0_bank1 = 1'b1;
+    case (addr0[ADDR_WIDTH - 1 : ADDR_WIDTH - BANK_SEL])
+      0: begin
+        web0_bank0 = web0;
+        csb0_bank0 = csb0;
+      end
+      1: begin
+        web0_bank1 = web0;
+        csb0_bank1 = csb0;
+      end
+    endcase
+  end
+
+
+endmodule