Move nmos gate to the top of the ptx.

2026-08-29 01:24:39 +02:00 · 2017-12-01 08:31:16 -08:00
parent 45ae8c7315
commit 8df46abb30
5 changed files with 89 additions and 70 deletions
@@ -67,7 +67,7 @@ layer["boundary"]= 239
 #technology parameter
 parameter={}
 parameter["min_tx_size"] = 0.09
-parameter["pinv_beta"] = 3
+parameter["beta"] = 3

 drclvs_home=os.environ.get("DRCLVS_HOME")
 drc={}
@@ -54,7 +54,7 @@ layer["boundary"]       = 83
 #technology parameter
 parameter={}
 parameter["min_tx_size"] = 1.2
-parameter["pinv_beta"] = 2 #for use in pinv
+parameter["beta"] = 2 

 drclvs_home=os.environ.get("DRCLVS_HOME")