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https://github.com/VLSIDA/OpenRAM.git
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scmos passing with odd sizses again
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@@ -12,6 +12,7 @@ from openram import OPTS
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from .bitcell_base_array import bitcell_base_array
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from .pattern import pattern
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from openram.base import geometry, instance
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from math import ceil
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class bitcell_array(bitcell_base_array):
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"""
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@@ -60,18 +61,11 @@ class bitcell_array(bitcell_base_array):
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def create_instances(self):
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self.cell_inst={}
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core_block = [[0 for x in range(2)] for y in range(2)]
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core_block[0][0] = geometry.instance("core_0_0", mod=self.cell)
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core_block[0][1] = geometry.instance("core_1_0", mod=self.cell)
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core_block[1][0] = geometry.instance("core_0_1", mod=self.cell)
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core_block[1][1] = geometry.instance("core_1_1", mod=self.cell)
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num_core_x = self.row_size/len(core_block[0])
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num_core_y = self.column_size/len(core_block)
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debug.check(num_core_x.is_integer(), "number of core blocks must be an integer")
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debug.check(num_core_y.is_integer(), "number of core blocks must be an integer")
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num_core_x = int(num_core_x)
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num_core_y = int(num_core_y)
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self.pattern = pattern(self, "bitcell_array", core_block, num_core_x, num_core_y)
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core_block[0][0] = geometry.instance("core_0_0", mod=self.cell, is_bitcell=True)
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core_block[0][1] = geometry.instance("core_1_0", mod=self.cell, is_bitcell=True)
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core_block[1][0] = geometry.instance("core_0_1", mod=self.cell, is_bitcell=True)
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core_block[1][1] = geometry.instance("core_1_1", mod=self.cell, is_bitcell=True)
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self.pattern = pattern(self, "bitcell_array", core_block, self.row_size, self.column_size)
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self.pattern.connect_array()
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def analytical_power(self, corner, load):
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