Add inline_drclvs option for improved coverage

compiler/tests/30_openram_back_end_test.py

@@ -26,7 +26,7 @@ class openram_test(openram_test):
 
     def runTest(self):
         OPENRAM_HOME = os.path.abspath(os.environ.get("OPENRAM_HOME"))
-        globals.init_openram("{0}/tests/config_{1}".format(OPENRAM_HOME,OPTS.tech_name))
+        globals.init_openram("{0}/tests/config_{1}_back_end".format(OPENRAM_HOME,OPTS.tech_name))
 
         debug.info(1, "Testing top-level back-end openram.py with 2-bit, 16 word SRAM.")
         out_file = "testsram"

compiler/tests/config_freepdk45_back_end.py

@@ -0,0 +1,20 @@
+# See LICENSE for licensing information.
+#
+#Copyright (c) 2019 Regents of the University of California and The Board
+#of Regents for the Oklahoma Agricultural and Mechanical College
+#(acting for and on behalf of Oklahoma State University)
+#All rights reserved.
+#
+word_size = 1
+num_words = 16
+
+tech_name = "freepdk45"
+process_corners = ["TT"]
+supply_voltages = [1.0]
+temperatures = [25]
+
+inline_lvsdrc = True
+route_supplies = True
+check_lvsdrc = True
+
+

compiler/tests/config_scn4m_subm_back_end.py

@@ -0,0 +1,22 @@
+# See LICENSE for licensing information.
+#
+#Copyright (c) 2019 Regents of the University of California and The Board
+#of Regents for the Oklahoma Agricultural and Mechanical College
+#(acting for and on behalf of Oklahoma State University)
+#All rights reserved.
+#
+word_size = 1
+num_words = 16
+
+tech_name = "scn4m_subm"
+process_corners = ["TT"]
+supply_voltages = [5.0]
+temperatures = [25]
+
+route_supplies = True
+check_lvsdrc = True
+inline_lvsdrc = True
+
+drc_name = "magic"
+lvs_name = "netgen"
+pex_name = "magic"