mirror of
https://github.com/VLSIDA/OpenRAM.git
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Merge branch 'dev' into control_fix
This commit is contained in:
Matt Guthaus
@@ -945,40 +945,7 @@ class bank(design.design):
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self.add_wire(("metal1","via1","metal2"),[pin_pos, mid_pos, control_pos])
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self.add_via_center(layers=("metal1", "via1", "metal2"),
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offset=control_pos)
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def analytical_delay(self, corner, slew, load, port):
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""" return analytical delay of the bank. This will track the clock to output path"""
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#FIXME: This delay is determined in the control logic. Should be moved here.
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# word_driver_delay = self.wordline_driver.analytical_delay(corner,
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# slew,
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# self.bitcell_array.input_load())
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#FIXME: Array delay is the same for every port.
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word_driver_slew = 0
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if self.words_per_row > 1:
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bitline_ext_load = self.port_data[port].column_mux_array.get_drain_cin()
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else:
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bitline_ext_load = self.port_data[port].sense_amp_array.get_drain_cin()
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bitcell_array_delay = self.bitcell_array.analytical_delay(corner, word_driver_slew, bitline_ext_load)
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bitcell_array_slew = 0
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#This also essentially creates the same delay for each port. Good structure, no substance
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if self.words_per_row > 1:
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sa_load = self.port_data[port].sense_amp_array.get_drain_cin()
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column_mux_delay = self.port_data[port].column_mux_array.analytical_delay(corner,
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bitcell_array_slew,
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sa_load)
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else:
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column_mux_delay = []
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column_mux_slew = 0
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sense_amp_delay = self.port_data[port].sense_amp_array.analytical_delay(corner,
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column_mux_slew,
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load)
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# output load of bitcell_array is set to be only small part of bl for sense amp.
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return bitcell_array_delay + column_mux_delay + sense_amp_delay
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def determine_wordline_stage_efforts(self, external_cout, inp_is_rise=True):
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"""Get the all the stage efforts for each stage in the path within the bank clk_buf to a wordline"""
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#Decoder is assumed to have settled before the negative edge of the clock. Delay model relies on this assumption
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@@ -148,17 +148,7 @@ class bitcell_array(design.design):
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for pin_name in ["vdd", "gnd"]:
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for pin in inst.get_pins(pin_name):
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self.add_power_pin(name=pin_name, loc=pin.center(), vertical=True, start_layer=pin.layer)
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def analytical_delay(self, corner, slew, load):
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"""Returns relative delay of the bitline in the bitcell array"""
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from tech import parameter
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#The load being driven/drained is mostly the bitline but could include the sense amp or the column mux.
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#The load from the bitlines is due to the drain capacitances from all the other bitlines and wire parasitics.
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drain_load = logical_effort.convert_farad_to_relative_c(parameter['bitcell_drain_cap'])
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wire_unit_load = .05 * drain_load #Wires add 5% to this.
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bitline_load = (drain_load+wire_unit_load)*self.row_size
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return [self.cell.analytical_delay(corner, slew, load+bitline_load)]
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def analytical_power(self, corner, load):
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"""Power of Bitcell array and bitline in nW."""
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from tech import drc, parameter
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@@ -197,15 +187,6 @@ class bitcell_array(design.design):
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bl_wire.wire_c =spice["min_tx_drain_c"] + bl_wire.wire_c # 1 access tx d/s per cell
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return bl_wire
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def output_load(self, bl_pos=0):
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bl_wire = self.gen_bl_wire()
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return bl_wire.wire_c # sense amp only need to charge small portion of the bl
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# set as one segment for now
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def input_load(self):
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wl_wire = self.gen_wl_wire()
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return wl_wire.return_input_cap()
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def get_wordline_cin(self):
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"""Get the relative input capacitance from the wordline connections in all the bitcell"""
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#A single wordline is connected to all the bitcells in a single row meaning the capacitance depends on the # of columns
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@@ -924,7 +924,8 @@ class control_logic(design.design):
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last_stage_rise = False
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#First stage(s), clk -(pdriver)-> clk_buf.
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clk_buf_cout = self.replica_bitline.get_en_cin()
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#clk_buf_cout = self.replica_bitline.get_en_cin()
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clk_buf_cout = 0
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stage_effort_list += self.clk_buf_driver.get_stage_efforts(clk_buf_cout, last_stage_rise)
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last_stage_rise = stage_effort_list[-1].is_rise
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@@ -48,11 +48,6 @@ class dff(design.design):
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transition_prob = spice["flop_transition_prob"]
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return transition_prob*(c_load + c_para)
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def analytical_delay(self, corner, slew, load = 0.0):
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# dont know how to calculate this now, use constant in tech file
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result = self.return_delay(spice["dff_delay"], spice["dff_slew"])
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return result
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def get_clk_cin(self):
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"""Return the total capacitance (in relative units) that the clock is loaded by in the dff"""
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#This is a handmade cell so the value must be entered in the tech.py file or estimated.
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@@ -160,11 +160,6 @@ class dff_array(design.design):
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self.add_via_center(layers=("metal2","via2","metal3"),
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offset=vector(clk_pin.cx(),clk_ypos))
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def analytical_delay(self, corner, slew, load=0.0):
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return self.dff.analytical_delay(corner, slew=slew, load=load)
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def get_clk_cin(self):
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"""Return the total capacitance (in relative units) that the clock is loaded by in the dff array"""
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dff_clk_cin = self.dff.get_clk_cin()
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@@ -177,16 +177,7 @@ class dff_buf(design.design):
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self.add_path("metal1", [self.mid_qb_pos, qb_pos])
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self.add_via_center(layers=("metal1","via1","metal2"),
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offset=qb_pos)
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def analytical_delay(self, corner, slew, load=0.0):
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""" Calculate the analytical delay of DFF-> INV -> INV """
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dff_delay=self.dff.analytical_delay(corner, slew=slew, load=self.inv1.input_load())
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inv1_delay = self.inv1.analytical_delay(corner, slew=dff_delay.slew, load=self.inv2.input_load())
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inv2_delay = self.inv2.analytical_delay(corner, slew=inv1_delay.slew, load=load)
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return dff_delay + inv1_delay + inv2_delay
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def get_clk_cin(self):
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"""Return the total capacitance (in relative units) that the clock is loaded by in the dff"""
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#This is a handmade cell so the value must be entered in the tech.py file or estimated.
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@@ -193,11 +193,6 @@ class dff_buf_array(design.design):
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self.add_via_center(layers=("metal2","via2","metal3"),
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offset=vector(clk_pin.cx(),clk_ypos))
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def analytical_delay(self, corner, slew, load=0.0):
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return self.dff.analytical_delay(slew=slew, load=load)
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def get_clk_cin(self):
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"""Return the total capacitance (in relative units) that the clock is loaded by in the dff array"""
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dff_clk_cin = self.dff.get_clk_cin()
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@@ -150,15 +150,7 @@ class dff_inv(design.design):
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offset=dout_pin.center())
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self.add_via_center(layers=("metal1","via1","metal2"),
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offset=dout_pin.center())
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def analytical_delay(self, corner, slew, load=0.0):
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""" Calculate the analytical delay of DFF-> INV -> INV """
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dff_delay=self.dff.analytical_delay(corner, slew=slew, load=self.inv1.input_load())
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inv1_delay = self.inv1.analytical_delay(corner, slew=dff_delay.slew, load=load)
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return dff_delay + inv1_delay
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def get_clk_cin(self):
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"""Return the total capacitance (in relative units) that the clock is loaded by in the dff"""
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return self.dff.get_clk_cin()
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@@ -190,12 +190,6 @@ class dff_inv_array(design.design):
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self.add_via_center(layers=("metal2","via2","metal3"),
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offset=vector(clk_pin.cx(),clk_ypos))
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def analytical_delay(self, corner, slew, load=0.0):
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return self.dff.analytical_delay(corner, slew=slew, load=load)
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def get_clk_cin(self):
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"""Return the total capacitance (in relative units) that the clock is loaded by in the dff array"""
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dff_clk_cin = self.dff.get_clk_cin()
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@@ -596,28 +596,6 @@ class hierarchical_decoder(design.design):
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self.add_via_center(layers=("metal2", "via2", "metal3"),
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offset=rail_pos)
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def analytical_delay(self, corner, slew, load = 0.0):
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# A -> out
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if self.determine_predecodes(self.num_inputs)[1]==0:
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pre = self.pre2_4
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nand = self.nand2
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else:
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pre = self.pre3_8
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nand = self.nand3
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a_t_out_delay = pre.analytical_delay(corner, slew=slew,load = nand.input_load())
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# out -> z
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out_t_z_delay = nand.analytical_delay(corner, slew= a_t_out_delay.slew,
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load = self.inv.input_load())
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result = a_t_out_delay + out_t_z_delay
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# Z -> decode_out
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z_t_decodeout_delay = self.inv.analytical_delay(corner, slew = out_t_z_delay.slew , load = load)
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result = result + z_t_decodeout_delay
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return result
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def input_load(self):
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if self.determine_predecodes(self.num_inputs)[1]==0:
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pre = self.pre2_4
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@@ -56,21 +56,4 @@ class hierarchical_predecode2x4(hierarchical_predecode):
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["A_0", "Abar_1"],
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["Abar_0", "A_1"],
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["A_0", "A_1"]]
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return combination
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def analytical_delay(self, corner, slew, load = 0.0 ):
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# in -> inbar
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a_t_b_delay = self.inv.analytical_delay(corner, slew=slew, load=self.nand.input_load())
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# inbar -> z
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b_t_z_delay = self.nand.analytical_delay(corner, slew=a_t_b_delay.slew, load=self.inv.input_load())
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# Z -> out
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a_t_out_delay = self.inv.analytical_delay(corner, slew=b_t_z_delay.slew, load=load)
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return a_t_b_delay + b_t_z_delay + a_t_out_delay
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def input_load(self):
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return self.nand.input_load()
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return combination
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@@ -65,21 +65,4 @@ class hierarchical_predecode3x8(hierarchical_predecode):
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["A_0", "Abar_1", "A_2"],
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["Abar_0", "A_1", "A_2"],
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["A_0", "A_1", "A_2"]]
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return combination
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def analytical_delay(self, corner, slew, load = 0.0 ):
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# A -> Abar
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a_t_b_delay = self.inv.analytical_delay(corner, slew=slew, load=self.nand.input_load())
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# Abar -> z
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b_t_z_delay = self.nand.analytical_delay(corner, slew=a_t_b_delay.slew, load=self.inv.input_load())
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# Z -> out
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a_t_out_delay = self.inv.analytical_delay(corner, slew=b_t_z_delay.slew, load=load)
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return a_t_b_delay + b_t_z_delay + a_t_out_delay
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def input_load(self):
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return self.nand.input_load()
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return combination
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@@ -827,22 +827,4 @@ class multibank(design.design):
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rotate=90)
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self.add_via(layers=("metal2","via2","metal3"),
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offset=in_pin + self.m2m3_via_offset,
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rotate=90)
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def analytical_delay(self, corner, slew, load):
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""" return analytical delay of the bank"""
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decoder_delay = self.row_decoder.analytical_delay(corner, slew, self.wordline_driver.input_load())
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word_driver_delay = self.wordline_driver.analytical_delay(corner, decoder_delay.slew, self.bitcell_array.input_load())
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bitcell_array_delay = self.bitcell_array.analytical_delay(corner, word_driver_delay.slew)
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bl_t_data_out_delay = self.sense_amp_array.analytical_delay(corner, bitcell_array_delay.slew,
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self.bitcell_array.output_load())
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# output load of bitcell_array is set to be only small part of bl for sense amp.
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data_t_DATA_delay = self.tri_gate_array.analytical_delay(corner, bl_t_data_out_delay.slew, load)
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result = decoder_delay + word_driver_delay + bitcell_array_delay + bl_t_data_out_delay + data_t_DATA_delay
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return result
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rotate=90)
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@@ -373,17 +373,7 @@ class replica_bitcell_array(design.design):
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def get_rbl_br_name(self, port):
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""" Return the BR for the given RBL port """
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return self.rbl_br_names[port]
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def analytical_delay(self, corner, slew, load):
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"""Returns relative delay of the bitline in the bitcell array"""
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from tech import parameter
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#The load being driven/drained is mostly the bitline but could include the sense amp or the column mux.
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#The load from the bitlines is due to the drain capacitances from all the other bitlines and wire parasitics.
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drain_load = logical_effort.convert_farad_to_relative_c(parameter['bitcell_drain_cap'])
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wire_unit_load = 0.05 * drain_load #Wires add 5% to this.
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bitline_load = (drain_load+wire_unit_load)*self.row_size
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return [self.cell.analytical_delay(corner, slew, load+bitline_load)]
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def analytical_power(self, corner, load):
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"""Power of Bitcell array and bitline in nW."""
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from tech import drc, parameter
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||||
@@ -403,15 +393,6 @@ class replica_bitcell_array(design.design):
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cell_power.leakage * self.column_size * self.row_size)
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return total_power
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def gen_wl_wire(self):
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if OPTS.netlist_only:
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width = 0
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else:
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width = self.width
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wl_wire = self.generate_rc_net(int(self.column_size), width, drc("minwidth_metal1"))
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wl_wire.wire_c = 2*spice["min_tx_gate_c"] + wl_wire.wire_c # 2 access tx gate per cell
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return wl_wire
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def gen_bl_wire(self):
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if OPTS.netlist_only:
|
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height = 0
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@@ -422,15 +403,6 @@ class replica_bitcell_array(design.design):
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bl_wire.wire_c =spice["min_tx_drain_c"] + bl_wire.wire_c # 1 access tx d/s per cell
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return bl_wire
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def output_load(self, bl_pos=0):
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bl_wire = self.gen_bl_wire()
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return bl_wire.wire_c # sense amp only need to charge small portion of the bl
|
||||
# set as one segment for now
|
||||
|
||||
def input_load(self):
|
||||
wl_wire = self.gen_wl_wire()
|
||||
return wl_wire.return_input_cap()
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|
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def get_wordline_cin(self):
|
||||
"""Get the relative input capacitance from the wordline connections in all the bitcell"""
|
||||
#A single wordline is connected to all the bitcells in a single row meaning the capacitance depends on the # of columns
|
||||
|
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@@ -33,15 +33,18 @@ class sense_amp(design.design):
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||||
self.pin_map = sense_amp.pin_map
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self.add_pin_types(self.type_list)
|
||||
|
||||
def input_load(self):
|
||||
def get_cin(self):
|
||||
|
||||
# FIXME: This input load will be applied to both the s_en timing and bitline timing.
|
||||
|
||||
#Input load for the bitlines which are connected to the source/drain of a TX. Not the selects.
|
||||
from tech import spice, parameter
|
||||
# Default is 8x. Per Samira and Hodges-Jackson book:
|
||||
# "Column-mux transistors driven by the decoder must be sized for optimal speed"
|
||||
bitline_pmos_size = 8 #FIXME: This should be set somewhere and referenced. Probably in tech file.
|
||||
return spice["min_tx_drain_c"]*(bitline_pmos_size/parameter["min_tx_size"])#ff
|
||||
return spice["min_tx_drain_c"]*(bitline_pmos_size)#ff
|
||||
|
||||
def analytical_delay(self, corner, slew, load):
|
||||
def get_stage_effort(self, load):
|
||||
#Delay of the sense amp will depend on the size of the amp and the output load.
|
||||
parasitic_delay = 1
|
||||
cin = (parameter["sa_inv_pmos_size"] + parameter["sa_inv_nmos_size"])/drc("minwidth_tx")
|
||||
|
||||
@@ -144,10 +144,7 @@ class sense_amp_array(design.design):
|
||||
|
||||
def input_load(self):
|
||||
return self.amp.input_load()
|
||||
|
||||
def analytical_delay(self, corner, slew, load):
|
||||
return [self.amp.analytical_delay(corner, slew=slew, load=load)]
|
||||
|
||||
|
||||
def get_en_cin(self):
|
||||
"""Get the relative capacitance of all the sense amp enable connections in the array"""
|
||||
sense_amp_en_cin = self.amp.get_en_cin()
|
||||
|
||||
@@ -210,15 +210,6 @@ class single_level_column_mux_array(design.design):
|
||||
self.add_via_center(layers=("metal1", "via1", "metal2"),
|
||||
offset=br_out_offset)
|
||||
|
||||
|
||||
def analytical_delay(self, corner, slew, load):
|
||||
from tech import parameter
|
||||
"""Returns relative delay that the column mux adds"""
|
||||
#Single level column mux will add parasitic loads from other mux pass transistors and the sense amp.
|
||||
drain_load = logical_effort.convert_farad_to_relative_c(parameter['bitcell_drain_cap'])
|
||||
array_load = drain_load*self.words_per_row
|
||||
return [self.mux.analytical_delay(corner, slew, load+array_load)]
|
||||
|
||||
def get_drain_cin(self):
|
||||
"""Get the relative capacitance of the drain of the NMOS pass TX"""
|
||||
from tech import parameter
|
||||
|
||||
@@ -12,7 +12,7 @@ from tech import GDS,layer
|
||||
|
||||
class tri_gate(design.design):
|
||||
"""
|
||||
This module implements the tri gate cell used in the design for
|
||||
This module implements the tri gate cell used in the design forS
|
||||
bit-line isolation. It is a hand-made cell, so the layout and
|
||||
netlist should be available in the technology library.
|
||||
"""
|
||||
@@ -36,19 +36,13 @@ class tri_gate(design.design):
|
||||
self.pin_map = tri_gate.pin_map
|
||||
self.add_pin_types(self.type_list)
|
||||
|
||||
def analytical_delay(self, corner, slew, load=0.0):
|
||||
from tech import spice
|
||||
r = spice["min_tx_r"]
|
||||
c_para = spice["min_tx_drain_c"]
|
||||
return self.cal_delay_with_rc(corner, r = r, c = c_para+load, slew = slew)
|
||||
|
||||
def analytical_power(self, corner, load):
|
||||
"""Returns dynamic and leakage power. Results in nW"""
|
||||
#Power in this module currently not defined. Returns 0 nW (leakage and dynamic).
|
||||
total_power = self.return_power()
|
||||
return total_power
|
||||
|
||||
def input_load(self):
|
||||
def get_cin(self):
|
||||
return 9*spice["min_tx_gate_c"]
|
||||
|
||||
def build_graph(self, graph, inst_name, port_nets):
|
||||
|
||||
@@ -120,10 +120,4 @@ class tri_gate_array(design.design):
|
||||
layer="metal1",
|
||||
offset=enbar_pin.ll().scale(0, 1),
|
||||
width=width,
|
||||
height=drc("minwidth_metal1"))
|
||||
|
||||
|
||||
|
||||
def analytical_delay(self, corner, slew, load=0.0):
|
||||
return self.tri.analytical_delay(corner, slew = slew, load = load)
|
||||
|
||||
height=drc("minwidth_metal1"))
|
||||
@@ -210,21 +210,6 @@ class wordline_driver(design.design):
|
||||
start=wl_offset,
|
||||
end=wl_offset-vector(self.m1_width,0))
|
||||
|
||||
|
||||
def analytical_delay(self, corner, slew, load=0):
|
||||
# decode -> net
|
||||
decode_t_net = self.nand2.analytical_delay(corner, slew, self.inv.input_load())
|
||||
|
||||
# net -> wl
|
||||
net_t_wl = self.inv.analytical_delay(corner, decode_t_net.slew, load)
|
||||
|
||||
return decode_t_net + net_t_wl
|
||||
|
||||
|
||||
def input_load(self):
|
||||
"""Gets the capacitance of the wordline driver in absolute units (fF)"""
|
||||
return self.nand2.input_load()
|
||||
|
||||
def determine_wordline_stage_efforts(self, external_cout, inp_is_rise=True):
|
||||
"""Follows the clk_buf to a wordline signal adding each stages stage effort to a list"""
|
||||
stage_effort_list = []
|
||||
|
||||
Reference in New Issue
Block a user