luke/OpenRAM
1
0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-09-02 02:57:53 +02:00
Code Issues Packages Projects Releases Wiki Activity

Fix import issue

Browse Source
This commit is contained in:
Bugra Onal
2023-04-12 11:48:20 -07:00
parent 249d1b9c1d
commit 8d0c46d069
1 changed files with 1 additions and 3 deletions
Download Patch File Download Diff File Expand all files Collapse all files
compiler/characterizer/delay.py
+1 -3
View File
@@ -13,8 +13,6 @@ from openram import OPTS
from .stimuli import *
from .trim_spice import *
from .charutils import *
from .sram_op import *
from .bit_polarity import *
from .simulation import simulation
from .measurements import *
from os import path
@@ -1282,7 +1280,7 @@ class delay(simulation):
self.sen_name = "X{0}{1}xbank0{1}s_en".format(self.sram.name, OPTS.hier_seperator)
if not replica_bitcell_array_name:
replica_bitcell_array_name = "bitcell_array"
self.cell_format = "X{{0}}{{3}}xbank0{{3}}x{0}{{3}}xbitcell_array{{3}}xbit_r{{1}}_c{{2}}".format(replica_bitcell_array_name)
self.cell_format = "X{{0}}{{3}}xbank0{{3}}xbitcell_array{{3}}x{0}{{3}}xbitcell_array{{3}}xbit_r{{1}}_c{{2}}".format(replica_bitcell_array_name)
def analysis_init(self, probe_address, probe_data):
"""Sets values which are dependent on the data address/bit being tested."""