Connect dnwell taps to gnd

compiler/base/hierarchy_layout.py

@@ -1378,6 +1378,12 @@ class layout():
         layer_stack = self.active_stack
         tap_spacing = 2
         nwell_offset = vector(self.nwell_width, self.nwell_width)
+
+        # Every nth tap is connected to gnd
+        period = 5
+
+        # BOTTOM
+        count = 0
         loc = ll + nwell_offset.scale(tap_spacing, 0)
         end_loc = lr - nwell_offset.scale(tap_spacing, 0)
         while loc.x < end_loc.x:
@@ -1385,11 +1391,19 @@ class layout():
                                 offset=loc,
                                 implant_type="n",
                                 well_type="n")
+            if count % period:
                 self.add_via_stack_center(from_layer="li",
                                           to_layer="m1",
                                           offset=loc)
+            else:
+                self.add_power_pin(name="gnd",
+                                   loc=loc,
+                                   start_layer="li")
+            count += 1
             loc += nwell_offset.scale(tap_spacing, 0)
 
+        # TOP
+        count = 0
         loc = ul + nwell_offset.scale(tap_spacing, 0)
         end_loc = ur - nwell_offset.scale(tap_spacing, 0)
         while loc.x < end_loc.x:
@@ -1397,11 +1411,19 @@ class layout():
                                 offset=loc,
                                 implant_type="n",
                                 well_type="n")
+            if count % period:
                 self.add_via_stack_center(from_layer="li",
-                                      to_layer="m2",
+                                          to_layer="m1",
                                           offset=loc)
+            else:
+                self.add_power_pin(name="gnd",
+                                   loc=loc,
+                                   start_layer="li")
+            count += 1
             loc += nwell_offset.scale(tap_spacing, 0)
 
+        # LEFT
+        count = 0
         loc = ll + nwell_offset.scale(0, tap_spacing)
         end_loc = ul - nwell_offset.scale(0, tap_spacing)
         while loc.y < end_loc.y:
@@ -1409,11 +1431,19 @@ class layout():
                                 offset=loc,
                                 implant_type="n",
                                 well_type="n")
+            if count % period:
                 self.add_via_stack_center(from_layer="li",
                                           to_layer="m2",
                                           offset=loc)
+            else:
+                self.add_power_pin(name="gnd",
+                                   loc=loc,
+                                   start_layer="li")
+            count += 1
             loc += nwell_offset.scale(0, tap_spacing)
 
+        # RIGHT
+        count = 0
         loc = lr + nwell_offset.scale(0, tap_spacing)
         end_loc = ur - nwell_offset.scale(0, tap_spacing)
         while loc.y < end_loc.y:
@@ -1421,9 +1451,15 @@ class layout():
                                 offset=loc,
                                 implant_type="n",
                                 well_type="n")
+            if count % period:
                 self.add_via_stack_center(from_layer="li",
                                           to_layer="m2",
                                           offset=loc)
+            else:
+                self.add_power_pin(name="gnd",
+                                   loc=loc,
+                                   start_layer="li")
+            count += 1
             loc += nwell_offset.scale(0, tap_spacing)
 
         # Add the gnd ring

compiler/base/lef.py

@@ -110,7 +110,8 @@ class lef:
 
         # For each pin, remove the blockage and add the pin
         for pin_name in self.pins:
-            pin = self.get_pin(pin_name)
+            pins = self.get_pins(pin_name)
+            for pin in pins:
                 inflated_pin = pin.inflated_pin(multiple=1)
                 another_iteration_needed = True
                 while another_iteration_needed:

compiler/router/router.py

@@ -898,7 +898,7 @@ class router(router_tech):
         Adds a supply pin to the perimeter and resizes the bounding box.
         """
         pg = pin_group(name, [], self)
-        if name == "vdd":
+        if name == "gnd":
             offset = width + 1
         else:
             offset = 1
@@ -927,7 +927,7 @@ class router(router_tech):
         pg = pin_group(name, [], self)
         # Offset the vdd inside one ring width
         # Units are in routing grids
-        if name == "vdd":
+        if name == "gnd":
             offset = width + 1
         else:
             offset = 1

compiler/sram/sram_base.py

@@ -209,7 +209,7 @@ class sram_base(design, verilog, lef):
 
         self.add_lvs_correspondence_points()
 
-        #self.offset_all_coordinates()
+        self.offset_all_coordinates()
 
         highest_coord = self.find_highest_coords()
         self.width = highest_coord[0]