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https://github.com/VLSIDA/OpenRAM.git
synced 2026-09-03 08:13:16 +02:00
remove end caps from replica column (will not pass sky130 drc)
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@@ -26,19 +26,19 @@ class replica_column_test(openram_test):
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globals.setup_bitcell()
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debug.info(2, "Testing one left replica column for dual port")
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a = factory.create(module_type="replica_column", rows=4, rbl=[1, 0], replica_bit=1)
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a = factory.create(module_type="replica_column", rows=4, rbl=[1, 0], replica_bit=0)
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self.local_check(a)
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debug.info(2, "Testing one right replica column for dual port")
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a = factory.create(module_type="replica_column", rows=4, rbl=[0, 1], replica_bit=5)
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a = factory.create(module_type="replica_column", rows=4, rbl=[0, 1], replica_bit=4)
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self.local_check(a)
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debug.info(2, "Testing two (left, right) replica columns for dual port")
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a = factory.create(module_type="replica_column", rows=4, rbl=[1, 1], replica_bit=1)
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a = factory.create(module_type="replica_column", rows=4, rbl=[1, 1], replica_bit=0)
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self.local_check(a)
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debug.info(2, "Testing two (left, right) replica columns for dual port")
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a = factory.create(module_type="replica_column", rows=4, rbl=[1, 1], replica_bit=6)
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a = factory.create(module_type="replica_column", rows=4, rbl=[1, 1], replica_bit=5)
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self.local_check(a)
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globals.end_openram()
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@@ -30,7 +30,7 @@ class replica_column_test(openram_test):
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a = factory.create(module_type="replica_column",
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rows=4 + num_spare_rows,
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rbl=[1, 0],
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replica_bit=1,
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replica_bit=0,
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column_offset=num_spare_cols)
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self.local_check(a)
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