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Improvements to power routing.

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Improved the route horizontal and vertical pin functions to
create a single pin at the end.
Swapped A and B on wordline driver input for cleaner routing
in most technologies.
Fixed vertical supply routing in port_address.
This commit is contained in:
mrg
2022-03-04 15:44:07 -08:00
parent 10bec414e8
commit 8b3c10ae79
5 changed files with 92 additions and 59 deletions
Download Patch File Download Diff File Expand all files Collapse all files
compiler/modules/hierarchical_decoder.py
+6 -6
View File
@@ -596,10 +596,10 @@ class hierarchical_decoder(design.design):
"""
if layer_props.hierarchical_decoder.vertical_supply:
pre_insts = self.pre2x4_inst + self.pre3x8_inst + self.pre4x16_inst
self.route_vertical_pins("vdd", insts=pre_insts)
self.route_vertical_pins("gnd", insts=pre_insts)
self.route_vertical_pins("vdd", insts=self.and_inst)
self.route_vertical_pins("gnd", insts=self.and_inst)
self.route_vertical_pins("vdd", insts=pre_insts, yside="by")
self.route_vertical_pins("gnd", insts=pre_insts, yside="by")
self.route_vertical_pins("vdd", insts=self.and_inst, yside="by")
self.route_vertical_pins("gnd", insts=self.and_inst, yside="by")
return
for n in ["vdd", "gnd"]:
pins = self.and_inst[0].get_pins(n)
@@ -622,8 +622,8 @@ class hierarchical_decoder(design.design):
pre_insts = self.pre2x4_inst + self.pre3x8_inst + self.pre4x16_inst
self.route_vertical_pins("vdd", insts=pre_insts)
self.route_vertical_pins("gnd", insts=pre_insts)
self.route_vertical_pins("vdd", insts=self.and_inst, side="right")
self.route_vertical_pins("gnd", insts=self.and_inst, side="left")
self.route_vertical_pins("vdd", insts=self.and_inst, xside="rx")
self.route_vertical_pins("gnd", insts=self.and_inst, xside="lx")
# Widen the rails to cover any gap
for inst in self.and_inst:
compiler/modules/port_address.py
+5 -7
View File
@@ -228,17 +228,15 @@ class port_address(design.design):
wordline_driver_array_offset = vector(self.row_decoder_inst.rx(), 0)
self.wordline_driver_array_inst.place(wordline_driver_array_offset)
# The wordline driver also had an extra gap on the right, so use this offset
well_gap = 2 * drc("pwell_to_nwell") + drc("nwell_enclose_active")
x_offset = self.wordline_driver_array_inst.rx() - well_gap - self.rbl_driver.width
# This m4_pitch corresponds to the offset space for jog routing in the
# wordline_driver_array
rbl_driver_offset = wordline_driver_array_offset + vector(self.m4_pitch, 0)
if self.port == 0:
rbl_driver_offset = vector(x_offset,
0)
self.rbl_driver_inst.place(rbl_driver_offset, "MX")
else:
rbl_driver_offset = vector(x_offset,
self.wordline_driver_array.height)
rbl_driver_offset += vector(0,
self.wordline_driver_array.height)
self.rbl_driver_inst.place(rbl_driver_offset)
# Pass this up
compiler/modules/replica_bitcell_array.py
+5
View File
@@ -463,6 +463,11 @@ class replica_bitcell_array(bitcell_base_array):
supply_insts = self.dummy_col_insts + self.dummy_row_insts
for pin_name in self.supplies:
#self.route_vertical_pins(name=pin_name, insts=supply_insts)
self.route_horizontal_pins(name=pin_name, insts=supply_insts)
#self.route_vertical_pins(name=pin_name, insts=self.replica_col_insts)
#self.route_horizontal_pins(name=pin_name, insts=self.replica_col_insts)
for inst in supply_insts:
pin_list = inst.get_pins(pin_name)
for pin in pin_list:
compiler/modules/wordline_driver_array.py
+14 -12
View File
@@ -42,9 +42,16 @@ class wordline_driver_array(design.design):
self.route_layer = "li"
else:
self.route_layer = "m1"
self.place_drivers()
self.route_layout()
self.offset_x_coordinates()
self.offset_x_coordinates(vector(-self.m4_pitch, 0))
# Leave a well gap to separate the bitcell array well from this well
well_gap = 2 * drc("pwell_to_nwell") + drc("nwell_enclose_active")
self.width = self.wld_inst[-1].rx() + well_gap
self.height = self.wld_inst[-1].uy()
self.add_boundary()
self.route_vdd_gnd()
self.DRC_LVS()
@@ -73,8 +80,8 @@ class wordline_driver_array(design.design):
self.route_vertical_pins("vdd", insts=self.wld_inst)
self.route_vertical_pins("gnd", insts=self.wld_inst)
else:
self.route_vertical_pins("vdd", insts=self.wld_inst, side="left")
self.route_vertical_pins("gnd", insts=self.wld_inst, side="right")
self.route_vertical_pins("vdd", insts=self.wld_inst, xside="lx")
self.route_vertical_pins("gnd", insts=self.wld_inst, xside="rx")
# Widen the rails to cover any gap
for num in range(self.rows):
@@ -93,8 +100,8 @@ class wordline_driver_array(design.design):
# add and2
self.wld_inst.append(self.add_inst(name=name_and,
mod=self.wl_driver))
self.connect_inst(["en",
"in_{0}".format(row),
self.connect_inst(["in_{0}".format(row),
"en",
"wl_{0}".format(row),
"vdd", "gnd"])
@@ -114,18 +121,13 @@ class wordline_driver_array(design.design):
self.wld_inst[row].place(offset=and2_offset,
mirror=inst_mirror)
# Leave a well gap to separate the bitcell array well from this well
well_gap = 2 * drc("pwell_to_nwell") + drc("nwell_enclose_active")
self.width = self.wl_driver.width + well_gap
self.height = self.wl_driver.height * self.rows
def route_layout(self):
""" Route all of the signals """
# Wordline enable connection
en_pin = self.wld_inst[0].get_pin("B")
en_bottom_pos = vector(en_pin.cx(), 0)
en_top_pos = vector(en_pin.cx(), self.height)
en_top_pos = vector(en_pin.cx(), self.wld_inst[-1].uy())
en_pin = self.add_layout_pin_segment_center(text="en",
layer="m2",
start=en_bottom_pos,
@@ -135,7 +137,7 @@ class wordline_driver_array(design.design):
and_inst = self.wld_inst[row]
# Drop a via
b_pin = and_inst.get_pin("A")
b_pin = and_inst.get_pin("B")
self.add_via_stack_center(from_layer=b_pin.layer,
to_layer="m2",
offset=b_pin.center())