luke
/
OpenRAM
mirror of https://github.com/VLSIDA/OpenRAM.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

Fixed verilog filename double extension

This commit is contained in:
Bugra Onal 2022-07-08 17:01:30 -07:00
parent a87b40e1cb
commit 898a1f07f5
1 changed files with 5 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

8
compiler/modules/sram.py
View File

@ -62,11 +62,13 @@ class sram():
self.s.gds_write(name) self.s.gds_write(name)
def verilog_write(self, name): def verilog_write(self, name):
self.s.verilog_write(name + '_1bank.v')
if self.num_banks != 1: if self.num_banks != 1:
self.s.verilog_write(name[:-2] + '_1bank.v')
from sram_multibank import sram_multibank from sram_multibank import sram_multibank
mb = sram_multibank(self.s) mb = sram_multibank(self.s)
mb.verilog_write(name + '.v') mb.verilog_write(name)
else:
self.s.verilog_write(name)
def extended_config_write(self, name): def extended_config_write(self, name):
"""Dump config file with all options. """Dump config file with all options.
@ -171,7 +173,7 @@ class sram():
# Write a verilog model # Write a verilog model
start_time = datetime.datetime.now() start_time = datetime.datetime.now()
vname = OPTS.output_path + self.s.name vname = OPTS.output_path + self.s.name + '.v'
debug.print_raw("Verilog: Writing to {0}".format(vname)) debug.print_raw("Verilog: Writing to {0}".format(vname))
self.verilog_write(vname) self.verilog_write(vname)
print_time("Verilog", datetime.datetime.now(), start_time) print_time("Verilog", datetime.datetime.now(), start_time)