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Update modules to use variable bit offsets.
Bitcell arrays can return the bit offsets. Port data and submodules can use offsets for spacing. Default spacing for port data if no offsets given.
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@@ -206,3 +206,9 @@ class bitcell_base_array(design.design):
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mirror=dir_key)
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yoffset += self.cell.height
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xoffset += self.cell.width
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def get_column_offsets(self):
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"""
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Return an array of the x offsets of all the regular bits
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"""
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return [self.cell_inst[0, col].lx() for col in range(self.column_size)]
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