luke/OpenRAM
1
0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-08-30 18:02:23 +02:00
Code Issues Packages Projects Releases Wiki Activity

fix control logic pex labels with multiport

Browse Source
This commit is contained in:
Jesse Cirimelli-Low
2019-12-18 12:45:12 +00:00
parent f0958b0b11
commit 88d3da0b4a
1 changed files with 7 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files
compiler/sram/sram_base.py
+7 -5
View File
@@ -112,11 +112,13 @@ class sram_base(design, verilog, lef):
# add pex labels for control logic
for i in range (0,len(self.control_logic_insts)):
control_logic_offset = self.control_logic_insts[i].offset
for output in self.control_logic_insts[i].mod.output_list:
pin = self.control_logic_insts[i].mod.get_pin(output)
offset = [control_logic_offset[0] + pin.center()[0], control_logic_offset[1] + pin.center()[1]]
self.add_layout_pin_rect_center("{0}{1}".format(pin.name,i), "metal1", offset)
instance = self.control_logic_insts[i]
control_logic_offset = instance.offset
for output in instance.mod.output_list:
pin = instance.mod.get_pin(output)
pin.transform([0,0], instance.mirror, instance.rotate)
offset = [control_logic_offset[0] + pin.center()[0], control_logic_offset[1] + pin.center()[1]]
self.add_layout_pin_rect_center("{0}{1}".format(pin.name,i), "metal1", offset)