Add risc5 functional tests

compiler/tests/50_riscv_1k_1rw1r_func_test.py

@@ -0,0 +1,64 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys, os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+
+@unittest.skip("SKIPPING 50_riscv_func_test")
+class riscv_func_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+        OPTS.analytical_delay = False
+        OPTS.netlist_only = True
+        OPTS.trim_netlist = False
+
+        #OPTS.local_array_size = 16
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 1
+        OPTS.num_w_ports = 0
+        globals.setup_bitcell()
+
+        # This is a hack to reload the characterizer __init__ with the spice version
+        from importlib import reload
+        import characterizer
+        reload(characterizer)
+        from characterizer import functional
+        from sram_config import sram_config
+        c = sram_config(word_size=32,
+                        write_size=8,
+                        num_words=256,
+                        num_banks=1)
+
+        debug.info(1, "Functional test RISC-V memory"
+                   "{} bit words, {} words, {} words per row, {} banks".format(c.word_size,
+                                                                               c.num_words,
+                                                                               c.words_per_row,
+                                                                               c.num_banks))
+        s = factory.create(module_type="sram", sram_config=c)
+        corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
+        f = functional(s.s, corner=corner, cycles=100)
+        (fail, error) = f.run()
+        self.assertTrue(fail, error)
+
+        globals.end_openram()
+
+# instantiate a copy of the class to actually run the test
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/50_riscv_1k_1rw_func_test.py

@@ -0,0 +1,66 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys, os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+
+@unittest.skip("SKIPPING 50_riscv_func_test")
+class riscv_func_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+        OPTS.analytical_delay = False
+        OPTS.netlist_only = True
+        OPTS.trim_netlist = False
+
+        #OPTS.local_array_size = 16
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 0
+        OPTS.num_w_ports = 0
+        globals.setup_bitcell()
+
+        # This is a hack to reload the characterizer __init__ with the spice version
+        from importlib import reload
+        import characterizer
+        reload(characterizer)
+        from characterizer import functional
+        from sram_config import sram_config
+        c = sram_config(word_size=32,
+                        write_size=8,
+                        num_words=256,
+                        num_banks=1,
+                        num_spare_rows=1,
+                        num_spare_cols=1)
+
+        debug.info(1, "Functional test RISC-V memory"
+                   "{} bit words, {} words, {} words per row, {} banks".format(c.word_size,
+                                                                               c.num_words,
+                                                                               c.words_per_row,
+                                                                               c.num_banks))
+        s = factory.create(module_type="sram", sram_config=c)
+        corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
+        f = functional(s.s, corner=corner, cycles=3)
+        (fail, error) = f.run()
+        self.assertTrue(fail, error)
+
+        globals.end_openram()
+
+# instantiate a copy of the class to actually run the test
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/50_riscv_1rw1r_phys_test.py

@@ -16,7 +16,7 @@ from sram_factory import factory
 import debug
 
 
-@unittest.skip("SKIPPING 50_riscv_phys_test")
+# @unittest.skip("SKIPPING 50_riscv_phys_test")
 class riscv_phys_test(openram_test):
 
     def runTest(self):

compiler/tests/50_riscv_1rw_func_test.py

@@ -16,7 +16,7 @@ from sram_factory import factory
 import debug
 
 
-# @unittest.skip("SKIPPING 50_riscv_func_test")
+@unittest.skip("SKIPPING 50_riscv_func_test")
 class riscv_func_test(openram_test):
 
     def runTest(self):
@@ -46,7 +46,7 @@ class riscv_func_test(openram_test):
         from sram_config import sram_config
         c = sram_config(word_size=32,
                         write_size=8,
-                        num_words=32,
+                        num_words=64,
                         num_banks=1,
                         num_spare_cols=num_spare_cols,
                         num_spare_rows=num_spare_rows)

compiler/tests/50_riscv_1rw_phys_test.py

@@ -0,0 +1,62 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys, os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+
+# @unittest.skip("SKIPPING 50_riscv_phys_test")
+class riscv_phys_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+        from sram_config import sram_config
+
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 1
+        OPTS.num_w_ports = 0
+        OPTS.local_array_size = 16
+        globals.setup_bitcell()
+        OPTS.route_supplies = False
+        OPTS.perimeter_pins = False
+
+        c = sram_config(word_size=32,
+                        write_size=8,
+                        num_words=32,
+                        num_banks=1,
+                        num_spare_rows=1,
+                        num_spare_cols=1)
+        c.words_per_row=2
+        c.recompute_sizes()
+        debug.info(1, "Layout test for {}rw,{}r,{}w sram "
+                   "with {} bit words, {} words, {} words per "
+                   "row, {} banks".format(OPTS.num_rw_ports,
+                                          OPTS.num_r_ports,
+                                          OPTS.num_w_ports,
+                                          c.word_size,
+                                          c.num_words,
+                                          c.words_per_row,
+                                          c.num_banks))
+        a = factory.create(module_type="sram", sram_config=c)
+        self.local_check(a, final_verification=True)
+
+        globals.end_openram()
+
+# instantiate a copy of the class to actually run the test
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/50_riscv_2k_1rw1r_func_test.py

@@ -0,0 +1,64 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys, os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+
+@unittest.skip("SKIPPING 50_riscv_func_test")
+class riscv_func_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+        OPTS.analytical_delay = False
+        OPTS.netlist_only = True
+        OPTS.trim_netlist = False
+
+        #OPTS.local_array_size = 16
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 1
+        OPTS.num_w_ports = 0
+        globals.setup_bitcell()
+
+        # This is a hack to reload the characterizer __init__ with the spice version
+        from importlib import reload
+        import characterizer
+        reload(characterizer)
+        from characterizer import functional
+        from sram_config import sram_config
+        c = sram_config(word_size=32,
+                        write_size=8,
+                        num_words=512,
+                        num_banks=1)
+
+        debug.info(1, "Functional test RISC-V memory"
+                   "{} bit words, {} words, {} words per row, {} banks".format(c.word_size,
+                                                                               c.num_words,
+                                                                               c.words_per_row,
+                                                                               c.num_banks))
+        s = factory.create(module_type="sram", sram_config=c)
+        corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
+        f = functional(s.s, corner=corner, cycles=100)
+        (fail, error) = f.run()
+        self.assertTrue(fail, error)
+
+        globals.end_openram()
+
+# instantiate a copy of the class to actually run the test
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/50_riscv_2k_1rw_func_test.py

@@ -0,0 +1,66 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys, os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+
+@unittest.skip("SKIPPING 50_riscv_func_test")
+class riscv_func_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+        OPTS.analytical_delay = False
+        OPTS.netlist_only = True
+        OPTS.trim_netlist = False
+
+        #OPTS.local_array_size = 16
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 0
+        OPTS.num_w_ports = 0
+        globals.setup_bitcell()
+
+        # This is a hack to reload the characterizer __init__ with the spice version
+        from importlib import reload
+        import characterizer
+        reload(characterizer)
+        from characterizer import functional
+        from sram_config import sram_config
+        c = sram_config(word_size=32,
+                        write_size=8,
+                        num_words=512,
+                        num_banks=1,
+                        num_spare_rows=1,
+                        num_spare_cols=1)
+
+        debug.info(1, "Functional test RISC-V memory"
+                   "{} bit words, {} words, {} words per row, {} banks".format(c.word_size,
+                                                                               c.num_words,
+                                                                               c.words_per_row,
+                                                                               c.num_banks))
+        s = factory.create(module_type="sram", sram_config=c)
+        corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
+        f = functional(s.s, corner=corner, cycles=100)
+        (fail, error) = f.run()
+        self.assertTrue(fail, error)
+
+        globals.end_openram()
+
+# instantiate a copy of the class to actually run the test
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/50_riscv_4k_1rw1r_func_test.py

@@ -0,0 +1,64 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys, os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+
+@unittest.skip("SKIPPING 50_riscv_func_test")
+class riscv_func_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+        OPTS.analytical_delay = False
+        OPTS.netlist_only = True
+        OPTS.trim_netlist = False
+
+        #OPTS.local_array_size = 16
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 1
+        OPTS.num_w_ports = 0
+        globals.setup_bitcell()
+
+        # This is a hack to reload the characterizer __init__ with the spice version
+        from importlib import reload
+        import characterizer
+        reload(characterizer)
+        from characterizer import functional
+        from sram_config import sram_config
+        c = sram_config(word_size=32,
+                        write_size=8,
+                        num_words=1024,
+                        num_banks=1)
+
+        debug.info(1, "Functional test RISC-V memory"
+                   "{} bit words, {} words, {} words per row, {} banks".format(c.word_size,
+                                                                               c.num_words,
+                                                                               c.words_per_row,
+                                                                               c.num_banks))
+        s = factory.create(module_type="sram", sram_config=c)
+        corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
+        f = functional(s.s, corner=corner)
+        (fail, error) = f.run()
+        self.assertTrue(fail, error)
+
+        globals.end_openram()
+
+# instantiate a copy of the class to actually run the test
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/50_riscv_4k_1rw_func_test.py

@@ -0,0 +1,66 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys, os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+
+@unittest.skip("SKIPPING 50_riscv_func_test")
+class riscv_func_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+        OPTS.analytical_delay = False
+        OPTS.netlist_only = True
+        OPTS.trim_netlist = False
+
+        #OPTS.local_array_size = 16
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 0
+        OPTS.num_w_ports = 0
+        globals.setup_bitcell()
+
+        # This is a hack to reload the characterizer __init__ with the spice version
+        from importlib import reload
+        import characterizer
+        reload(characterizer)
+        from characterizer import functional
+        from sram_config import sram_config
+        c = sram_config(word_size=32,
+                        write_size=8,
+                        num_words=1024,
+                        num_banks=1,
+                        num_spare_rows=1,
+                        num_spare_cols=1)
+
+        debug.info(1, "Functional test RISC-V memory"
+                   "{} bit words, {} words, {} words per row, {} banks".format(c.word_size,
+                                                                               c.num_words,
+                                                                               c.words_per_row,
+                                                                               c.num_banks))
+        s = factory.create(module_type="sram", sram_config=c)
+        corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
+        f = functional(s.s, corner=corner)
+        (fail, error) = f.run()
+        self.assertTrue(fail, error)
+
+        globals.end_openram()
+
+# instantiate a copy of the class to actually run the test
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/50_riscv_512b_1rw1r_func_test.py

@@ -0,0 +1,64 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys, os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+
+@unittest.skip("SKIPPING 50_riscv_func_test")
+class riscv_func_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+        OPTS.analytical_delay = False
+        OPTS.netlist_only = True
+        OPTS.trim_netlist = False
+
+        #OPTS.local_array_size = 16
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 1
+        OPTS.num_w_ports = 0
+        globals.setup_bitcell()
+
+        # This is a hack to reload the characterizer __init__ with the spice version
+        from importlib import reload
+        import characterizer
+        reload(characterizer)
+        from characterizer import functional
+        from sram_config import sram_config
+        c = sram_config(word_size=32,
+                        write_size=8,
+                        num_words=128,
+                        num_banks=1)
+
+        debug.info(1, "Functional test RISC-V memory"
+                   "{} bit words, {} words, {} words per row, {} banks".format(c.word_size,
+                                                                               c.num_words,
+                                                                               c.words_per_row,
+                                                                               c.num_banks))
+        s = factory.create(module_type="sram", sram_config=c)
+        corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
+        f = functional(s.s, corner=corner, cycles=100)
+        (fail, error) = f.run()
+        self.assertTrue(fail, error)
+
+        globals.end_openram()
+
+# instantiate a copy of the class to actually run the test
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/50_riscv_512b_1rw_func_test.py

@@ -0,0 +1,66 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys, os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+
+@unittest.skip("SKIPPING 50_riscv_func_test")
+class riscv_func_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+        OPTS.analytical_delay = False
+        OPTS.netlist_only = True
+        OPTS.trim_netlist = False
+
+        #OPTS.local_array_size = 16
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 0
+        OPTS.num_w_ports = 0
+        globals.setup_bitcell()
+
+        # This is a hack to reload the characterizer __init__ with the spice version
+        from importlib import reload
+        import characterizer
+        reload(characterizer)
+        from characterizer import functional
+        from sram_config import sram_config
+        c = sram_config(word_size=32,
+                        write_size=8,
+                        num_words=128,
+                        num_banks=1,
+                        num_spare_rows=1,
+                        num_spare_cols=1)
+
+        debug.info(1, "Functional test RISC-V memory"
+                   "{} bit words, {} words, {} words per row, {} banks".format(c.word_size,
+                                                                               c.num_words,
+                                                                               c.words_per_row,
+                                                                               c.num_banks))
+        s = factory.create(module_type="sram", sram_config=c)
+        corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
+        f = functional(s.s, corner=corner, cycles=25)
+        (fail, error) = f.run()
+        self.assertTrue(fail, error)
+
+        globals.end_openram()
+
+# instantiate a copy of the class to actually run the test
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/50_riscv_8k_1rw1r_func_test.py

@@ -0,0 +1,64 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys, os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+
+@unittest.skip("SKIPPING 50_riscv_func_test")
+class riscv_func_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+        OPTS.analytical_delay = False
+        OPTS.netlist_only = True
+        OPTS.trim_netlist = False
+
+        OPTS.local_array_size = 16
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 1
+        OPTS.num_w_ports = 0
+        globals.setup_bitcell()
+
+        # This is a hack to reload the characterizer __init__ with the spice version
+        from importlib import reload
+        import characterizer
+        reload(characterizer)
+        from characterizer import functional
+        from sram_config import sram_config
+        c = sram_config(word_size=32,
+                        write_size=8,
+                        num_words=2048,
+                        num_banks=1)
+
+        debug.info(1, "Functional test RISC-V memory"
+                   "{} bit words, {} words, {} words per row, {} banks".format(c.word_size,
+                                                                               c.num_words,
+                                                                               c.words_per_row,
+                                                                               c.num_banks))
+        s = factory.create(module_type="sram", sram_config=c)
+        corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
+        f = functional(s.s, corner=corner, cycles=100)
+        (fail, error) = f.run()
+        self.assertTrue(fail, error)
+
+        globals.end_openram()
+
+# instantiate a copy of the class to actually run the test
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())

compiler/tests/50_riscv_8k_1rw_func_test.py

@@ -0,0 +1,66 @@
+#!/usr/bin/env python3
+# See LICENSE for licensing information.
+#
+# Copyright (c) 2016-2021 Regents of the University of California and The Board
+# of Regents for the Oklahoma Agricultural and Mechanical College
+# (acting for and on behalf of Oklahoma State University)
+# All rights reserved.
+#
+import unittest
+from testutils import *
+import sys, os
+sys.path.append(os.getenv("OPENRAM_HOME"))
+import globals
+from globals import OPTS
+from sram_factory import factory
+import debug
+
+
+@unittest.skip("SKIPPING 50_riscv_func_test")
+class riscv_func_test(openram_test):
+
+    def runTest(self):
+        config_file = "{}/tests/configs/config".format(os.getenv("OPENRAM_HOME"))
+        globals.init_openram(config_file)
+        OPTS.analytical_delay = False
+        OPTS.netlist_only = True
+        OPTS.trim_netlist = False
+
+        OPTS.local_array_size = 16
+        OPTS.num_rw_ports = 1
+        OPTS.num_r_ports = 0
+        OPTS.num_w_ports = 0
+        globals.setup_bitcell()
+
+        # This is a hack to reload the characterizer __init__ with the spice version
+        from importlib import reload
+        import characterizer
+        reload(characterizer)
+        from characterizer import functional
+        from sram_config import sram_config
+        c = sram_config(word_size=32,
+                        write_size=8,
+                        num_words=2048,
+                        num_banks=1,
+                        num_spare_rows=1,
+                        num_spare_cols=1)
+
+        debug.info(1, "Functional test RISC-V memory"
+                   "{} bit words, {} words, {} words per row, {} banks".format(c.word_size,
+                                                                               c.num_words,
+                                                                               c.words_per_row,
+                                                                               c.num_banks))
+        s = factory.create(module_type="sram", sram_config=c)
+        corner = (OPTS.process_corners[0], OPTS.supply_voltages[0], OPTS.temperatures[0])
+        f = functional(s.s, corner=corner, cycles=100)
+        (fail, error) = f.run()
+        self.assertTrue(fail, error)
+
+        globals.end_openram()
+
+# instantiate a copy of the class to actually run the test
+if __name__ == "__main__":
+    (OPTS, args) = globals.parse_args()
+    del sys.argv[1:]
+    header(__file__, OPTS.tech_name)
+    unittest.main(testRunner=debugTestRunner())