mirror of https://github.com/VLSIDA/OpenRAM.git
Modify LEF output to have all capital LAYER. Remove extra space before new lines.
This commit is contained in:
Matt Guthaus
parent
550eadfa82
commit
857b997367
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@ -47,7 +47,7 @@ class lef:
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self.lef.write(" OBS\n")
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for lay in self.layer:
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self.lef.write(" Layer {0} ; \n".format(lay))
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self.lef.write(" LAYER {0} ;\n".format(lay))
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self.writeObstruct(self.sr.name, lay, mirr = 1, angle = math.radians(float(0)), xyShift = (0, 0))
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self.lef.write(" END\n")
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@ -210,7 +210,7 @@ class lef:
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pin_layer_coord = self.pinLayerCoord(self.sr.name, pinName)
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for pinLayer in pin_layer_coord:
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lay = [key for key, value in tech.layer.iteritems() if value == pinLayer][0]
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self.lef.write(" Layer {0} ; \n".format(lay))
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self.lef.write(" LAYER {0} ;\n".format(lay))
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for pinCoord in pin_layer_coord[pinLayer]:
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self.writePinCoord(self.sr.name, pinName, pinLayer, pinCoord,
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mirr = 1,angle = math.radians(float(0)), xyShift = (0, 0))
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@ -9,7 +9,7 @@ MACRO sram_2_16_1_freepdk45
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USE POWER ;
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SHAPE ABUTMENT ;
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PORT
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Layer metal1 ;
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LAYER metal1 ;
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RECT 0.0325 0.0 0.7325 41.725 ;
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RECT 12.7675 0.0 13.4675 41.725 ;
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END
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@ -19,14 +19,14 @@ MACRO sram_2_16_1_freepdk45
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USE GROUND ;
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SHAPE ABUTMENT ;
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PORT
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Layer metal2 ;
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LAYER metal2 ;
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RECT 8.9225 0.0 9.6225 41.725 ;
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END
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END gnd
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PIN DATA[0]
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DIRECTION INOUT ;
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PORT
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Layer metal3 ;
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LAYER metal3 ;
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RECT 11.48 0.0 11.55 3.22 ;
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RECT 11.48 0.0 11.55 0.135 ;
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END
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@ -34,7 +34,7 @@ MACRO sram_2_16_1_freepdk45
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PIN DATA[1]
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DIRECTION INOUT ;
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PORT
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Layer metal3 ;
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LAYER metal3 ;
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RECT 12.185 0.0 12.255 3.22 ;
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RECT 12.185 0.0 12.255 0.135 ;
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END
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@ -42,62 +42,62 @@ MACRO sram_2_16_1_freepdk45
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PIN ADDR[0]
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DIRECTION INPUT ;
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PORT
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Layer metal3 ;
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LAYER metal3 ;
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RECT 0.0325 7.4525 1.015 7.5225 ;
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END
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END ADDR[0]
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PIN ADDR[1]
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DIRECTION INPUT ;
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PORT
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Layer metal3 ;
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LAYER metal3 ;
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RECT 0.0325 6.7475 1.015 6.8175 ;
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END
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END ADDR[1]
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PIN ADDR[2]
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DIRECTION INPUT ;
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PORT
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Layer metal3 ;
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LAYER metal3 ;
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RECT 0.0325 6.0425 1.015 6.1125 ;
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END
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END ADDR[2]
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PIN ADDR[3]
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DIRECTION INPUT ;
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PORT
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Layer metal3 ;
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LAYER metal3 ;
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RECT 0.0325 5.3375 1.015 5.4075 ;
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END
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END ADDR[3]
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PIN CSb
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DIRECTION INPUT ;
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PORT
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Layer metal3 ;
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LAYER metal3 ;
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RECT -5.4125 8.275 -5.3425 8.415 ;
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END
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END CSb
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PIN OEb
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DIRECTION INPUT ;
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PORT
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Layer metal3 ;
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LAYER metal3 ;
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RECT -4.0025 8.275 -3.9325 8.415 ;
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END
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END OEb
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PIN WEb
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DIRECTION INPUT ;
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PORT
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Layer metal3 ;
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LAYER metal3 ;
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RECT -4.7075 8.275 -4.6375 8.415 ;
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END
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END WEb
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PIN clk
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DIRECTION INPUT ;
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PORT
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Layer metal3 ;
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LAYER metal3 ;
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RECT -2.0525 8.275 9.7625 8.345 ;
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RECT -2.085 8.275 -2.015 8.41 ;
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END
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END clk
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OBS
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Layer metal1 ;
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LAYER metal1 ;
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RECT -0.545 26.2975 0.0325 26.3625 ;
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RECT 12.7675 0.0 13.4675 41.725 ;
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RECT 0.0325 0.0 0.7325 41.725 ;
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@ -7449,7 +7449,7 @@ MACRO sram_2_16_1_freepdk45
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RECT -1.0825 16.8675 -0.9475 16.9325 ;
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RECT -1.035 17.3375 -0.9 17.4025 ;
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RECT 0.0325 19.855 0.2375 19.99 ;
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Layer via1 ;
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LAYER via1 ;
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RECT 11.835 19.68 11.9 19.745 ;
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RECT 11.835 19.68 11.9 19.745 ;
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RECT 11.835 19.68 11.9 19.745 ;
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@ -9252,7 +9252,7 @@ MACRO sram_2_16_1_freepdk45
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RECT -1.0 17.3375 -0.935 17.4025 ;
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RECT 0.0325 19.89 0.0975 19.955 ;
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RECT 0.1725 19.89 0.2375 19.955 ;
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Layer metal2 ;
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LAYER metal2 ;
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RECT -0.35 19.855 0.0325 19.925 ;
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RECT 8.9225 0.0 9.6225 41.725 ;
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RECT 10.8125 0.0 10.8825 41.725 ;
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@ -11796,7 +11796,7 @@ MACRO sram_2_16_1_freepdk45
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RECT 0.0325 19.855 0.2375 19.99 ;
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RECT 8.9225 20.695 9.1275 20.83 ;
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RECT -0.415 20.695 -0.28 20.765 ;
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Layer via2 ;
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LAYER via2 ;
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RECT 11.475 18.79 11.545 18.86 ;
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RECT 12.18 18.79 12.25 18.86 ;
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RECT 11.48 9.87 11.55 9.94 ;
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@ -11845,7 +11845,7 @@ MACRO sram_2_16_1_freepdk45
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RECT 8.9225 20.73 8.9875 20.795 ;
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RECT 9.0625 20.73 9.1275 20.795 ;
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RECT -0.38 20.6975 -0.315 20.7625 ;
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Layer metal3 ;
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LAYER metal3 ;
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RECT -2.0525 8.275 9.7625 8.345 ;
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RECT -0.14 15.975 10.3925 16.045 ;
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RECT -0.14 8.415 10.1825 8.485 ;
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@ -9,7 +9,7 @@ MACRO sram_2_16_1_scn3me_subm
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USE POWER ;
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SHAPE ABUTMENT ;
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PORT
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Layer metal1 ;
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LAYER metal1 ;
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RECT 0.45 0.0 9.45 459.3 ;
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RECT 147.45 0.0 156.45 459.3 ;
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END
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@ -19,14 +19,14 @@ MACRO sram_2_16_1_scn3me_subm
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USE GROUND ;
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SHAPE ABUTMENT ;
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PORT
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Layer metal2 ;
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LAYER metal2 ;
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RECT 95.55 0.0 104.55 459.3 ;
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END
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END gnd
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PIN DATA[0]
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DIRECTION INOUT ;
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PORT
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Layer metal3 ;
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LAYER metal3 ;
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RECT 128.7 0.0 130.2 30.15 ;
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RECT 128.7 0.0 130.5 1.8 ;
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END
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@ -34,7 +34,7 @@ MACRO sram_2_16_1_scn3me_subm
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PIN DATA[1]
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DIRECTION INOUT ;
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PORT
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Layer metal3 ;
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LAYER metal3 ;
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RECT 138.9 0.0 140.4 30.15 ;
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RECT 138.9 0.0 140.7 1.8 ;
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END
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@ -42,62 +42,62 @@ MACRO sram_2_16_1_scn3me_subm
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PIN ADDR[0]
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DIRECTION INPUT ;
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PORT
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Layer metal3 ;
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LAYER metal3 ;
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RECT 0.45 73.95 17.55 75.45 ;
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END
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END ADDR[0]
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PIN ADDR[1]
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DIRECTION INPUT ;
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PORT
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Layer metal3 ;
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LAYER metal3 ;
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RECT 0.45 63.75 17.55 65.25 ;
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END
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END ADDR[1]
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PIN ADDR[2]
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DIRECTION INPUT ;
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PORT
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Layer metal3 ;
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LAYER metal3 ;
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RECT 0.45 53.55 17.55 55.05 ;
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END
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END ADDR[2]
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PIN ADDR[3]
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DIRECTION INPUT ;
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PORT
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Layer metal3 ;
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LAYER metal3 ;
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RECT 0.45 43.35 17.55 44.85 ;
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END
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END ADDR[3]
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PIN CSb
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DIRECTION INPUT ;
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PORT
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Layer metal3 ;
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LAYER metal3 ;
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RECT -62.1 86.4 -60.3 88.2 ;
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END
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END CSb
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PIN OEb
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DIRECTION INPUT ;
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PORT
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Layer metal3 ;
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LAYER metal3 ;
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RECT -41.7 86.4 -39.9 88.2 ;
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END
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END OEb
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PIN WEb
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DIRECTION INPUT ;
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PORT
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Layer metal3 ;
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LAYER metal3 ;
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RECT -51.9 86.4 -50.1 88.2 ;
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END
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END WEb
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PIN clk
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DIRECTION INPUT ;
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PORT
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Layer metal3 ;
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LAYER metal3 ;
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RECT -27.15 85.5 106.35 87.0 ;
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RECT -27.6 85.5 -25.8 87.3 ;
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END
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END clk
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OBS
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Layer metal1 ;
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LAYER metal1 ;
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RECT -10.2 293.55 0.45 294.45 ;
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RECT 147.45 0.0 156.45 459.3 ;
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RECT 0.45 0.0 9.45 459.3 ;
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@ -4773,7 +4773,7 @@ MACRO sram_2_16_1_scn3me_subm
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RECT -15.0 175.5 -13.8 176.7 ;
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RECT -15.0 180.0 -13.8 181.2 ;
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RECT 0.45 219.6 2.85 220.8 ;
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Layer via1 ;
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LAYER via1 ;
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RECT 125.25 209.7 125.85 210.3 ;
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RECT 134.25 209.7 134.85 210.3 ;
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RECT 126.15 200.4 126.75 201.0 ;
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@ -5392,7 +5392,7 @@ MACRO sram_2_16_1_scn3me_subm
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RECT -14.7 180.3 -14.1 180.9 ;
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RECT 0.75 219.9 1.35 220.5 ;
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RECT 1.95 219.9 2.55 220.5 ;
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Layer metal2 ;
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LAYER metal2 ;
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RECT -7.5 219.6 0.45 220.5 ;
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RECT 95.55 0.0 104.55 459.3 ;
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RECT 119.85 0.0 120.75 459.3 ;
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@ -6442,7 +6442,7 @@ MACRO sram_2_16_1_scn3me_subm
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RECT 0.45 219.6 2.85 220.8 ;
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RECT 95.85 230.7 98.55 231.9 ;
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RECT -8.1 230.7 -6.9 231.9 ;
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Layer via2 ;
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LAYER via2 ;
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RECT 125.55 152.7 126.15 153.3 ;
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RECT 135.75 152.7 136.35 153.3 ;
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RECT 129.15 32.4 129.75 33.0 ;
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@ -6489,7 +6489,7 @@ MACRO sram_2_16_1_scn3me_subm
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RECT 96.15 231.0 96.75 231.6 ;
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RECT 97.65 231.0 98.25 231.6 ;
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RECT -7.8 231.0 -7.2 231.6 ;
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Layer metal3 ;
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LAYER metal3 ;
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RECT -27.15 85.5 106.35 87.0 ;
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RECT -3.0 161.7 114.45 163.2 ;
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RECT -3.0 88.5 111.75 90.0 ;
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