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https://github.com/VLSIDA/OpenRAM.git
synced 2026-09-07 01:44:26 +02:00
modify char to work with older macro
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Bugra Onal
@@ -121,9 +121,9 @@ class delay(simulation):
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# Other measurements associated with the read port not included in the liberty file
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read_measures.append(self.create_bitline_measurement_objects())
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read_measures.append(self.create_debug_measurement_objects())
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read_measures.append(self.create_read_bit_measures())
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# TODO: Maybe don't do this here (?)
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if OPTS.top_process != "memchar":
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read_measures.append(self.create_read_bit_measures())
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read_measures.append(self.create_sen_and_bitline_path_measures())
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return read_measures
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@@ -168,8 +168,7 @@ class delay(simulation):
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write_measures = []
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write_measures.append(self.write_lib_meas)
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if OPTS.top_process != "memchar":
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write_measures.append(self.create_write_bit_measures())
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write_measures.append(self.create_write_bit_measures())
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return write_measures
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@@ -229,8 +228,11 @@ class delay(simulation):
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bit_col = self.get_data_bit_column_number(probe_address, probe_data)
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bit_row = self.get_address_row_number(probe_address)
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(cell_name, cell_inst) = self.sram.get_cell_name(self.sram.name, bit_row, bit_col)
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storage_names = cell_inst.mod.get_storage_net_names()
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#(cell_name, cell_inst) = self.sram.get_cell_name(self.sram.name, bit_row, bit_col)
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cell_name = OPTS.hier_seperator.join(("X" + self.sram.name, "xbank0", "xreplica_bitcell_array", "xbitcell_array", "xbit_r{}_c{}".format(bit_row, bit_col)))
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#cell_name = OPTS.hier_seperator.join(("X" + self.sram.name, "xbank0", "xbitcell_array", "xbitcell_array", "xbit_r{}_c{}".format(bit_row, bit_col)))
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storage_names = ("Q", "Q_bar")
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#storage_names = cell_inst.mod.get_storage_net_names()
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debug.check(len(storage_names) == 2, ("Only inverting/non-inverting storage nodes"
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"supported for characterization. Storage nets={0}").format(storage_names))
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if OPTS.use_pex and OPTS.pex_exe[0] != "calibre":
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@@ -859,7 +861,8 @@ class delay(simulation):
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result[port].update(read_port_dict)
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self.path_delays = self.check_path_measures()
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if self.sen_path_meas and self.bl_path_meas:
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self.path_delays = self.check_path_measures()
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return (True, result)
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@@ -950,7 +953,7 @@ class delay(simulation):
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def check_bitline_meas(self, v_discharged_bl, v_charged_bl):
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"""
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Checks the value of the discharging bitline. Confirms s_en timing errors.
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Returns true if the bitlines are at there expected value.
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Returns true if the bitlines are at there their value.
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"""
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# The inputs looks at discharge/charged bitline rather than left or right (bl/br)
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# Performs two checks, discharging bitline is at least 10% away from vdd and there is a
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@@ -1161,7 +1164,13 @@ class delay(simulation):
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shutil.copy(self.sp_file, self.sim_sp_file)
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def recover_measurment_objects(self):
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mf = open(path.join(OPTS.output_path, "delay_meas.sp"), "r")
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mf_path = path.join(OPTS.output_path, "delay_meas.sp")
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self.sen_path_meas = None
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self.bl_path_meas = None
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if not path.exists(mf_path):
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debug.info(1, "Delay measure file not found. Skipping measure recovery")
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return
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mf = open(mf_path, "r")
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measure_text = mf.read()
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port_iter = re.finditer(r"\* (Read|Write) ports (\d*)", measure_text)
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port_measure_lines = []
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@@ -1179,34 +1188,34 @@ class delay(simulation):
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self.read_meas_lists.append([])
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self.read_bit_meas = {bit_polarity.NONINVERTING: [], bit_polarity.INVERTING: []}
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self.write_bit_meas = {bit_polarity.NONINVERTING: [], bit_polarity.INVERTING: []}
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bit_measure_rule = re.compile(r"\.meas tran (v_q_a\d+_b\d+_(read|write)_(zero|one)\d+) FIND v\((.*)\) AT=(\d+(\.\d+)?)n")
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for measures in port_measure_lines:
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port_name = measures[0]
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text = measures[1]
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bit_measure_iter = bit_measure_rule.finditer(text)
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for bit_measure in bit_measure_iter:
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meas_name = bit_measure.group(1)
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read = bit_measure.group(2) == "read"
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cycle = bit_measure.group(3)
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probe = bit_measure.group(4)
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polarity = bit_polarity.NONINVERTING
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if "q_bar" in meas_name:
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polarity = bit_polarity.INVERTING
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meas = voltage_at_measure(meas_name, probe)
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if read:
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if cycle == "one":
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meas.meta_str = sram_op.READ_ONE
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else:
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meas.meta_str = sram_op.READ_ZERO
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self.read_bit_meas[polarity].append(meas)
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self.read_meas_lists[-1].append(meas)
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else:
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if cycle == "one":
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meas.meta_str = sram_op.WRITE_ONE
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else:
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meas.meta_str = sram_op.WRITE_ZERO
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self.write_bit_meas[polarity].append(meas)
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self.write_meas_lists[-1].append(meas)
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# bit_measure_rule = re.compile(r"\.meas tran (v_q_a\d+_b\d+_(read|write)_(zero|one)\d+) FIND v\((.*)\) AT=(\d+(\.\d+)?)n")
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# for measures in port_measure_lines:
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# port_name = measures[0]
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# text = measures[1]
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# bit_measure_iter = bit_measure_rule.finditer(text)
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# for bit_measure in bit_measure_iter:
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# meas_name = bit_measure.group(1)
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# read = bit_measure.group(2) == "read"
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# cycle = bit_measure.group(3)
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# probe = bit_measure.group(4)
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# polarity = bit_polarity.NONINVERTING
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# if "q_bar" in meas_name:
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# polarity = bit_polarity.INVERTING
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# meas = voltage_at_measure(meas_name, probe)
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# if read:
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# if cycle == "one":
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# meas.meta_str = sram_op.READ_ONE
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# else:
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# meas.meta_str = sram_op.READ_ZERO
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# self.read_bit_meas[polarity].append(meas)
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# self.read_meas_lists[-1].append(meas)
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# else:
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# if cycle == "one":
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# meas.meta_str = sram_op.WRITE_ONE
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# else:
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# meas.meta_str = sram_op.WRITE_ZERO
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# self.write_bit_meas[polarity].append(meas)
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# self.write_meas_lists[-1].append(meas)
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delay_path_rule = re.compile(r"\.meas tran delay_(.*)_to_(.*)_(sen|bl)_(id\d*) TRIG v\((.*)\) VAL=(\d+(\.\d+)?) (RISE|FALL)=(\d+) TD=(\d+(\.\d+)?)n TARG v\((.*)\) VAL=(\d+(\.\d+)?) (RISE|FALL)=(\d+) TD=(\d+(\.\d+)?)n")
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port = self.read_ports[0]
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@@ -1244,10 +1253,10 @@ class delay(simulation):
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self.set_probe(probe_address, probe_data)
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self.prepare_netlist()
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if OPTS.top_process == "memchar":
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# TODO: fix
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self.bl_name = "xsram:xbank0:bl_0_{}"
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self.br_name = "xsram:xbank0:br_0_{}"
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self.sen_name = "xsram:s_en"
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# TODO: guess the bl and br. It can be "bl_..." or "bl..."
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self.bl_name = "X{0}{1}xbank0{1}bl{{}}_{2}".format(self.sram.name, OPTS.hier_seperator, self.bitline_column)
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self.br_name = "X{0}{1}xbank0{1}br{{}}_{2}".format(self.sram.name, OPTS.hier_seperator, self.bitline_column)
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self.sen_name = "X{0}{1}xbank0{1}s_en".format(self.sram.name, OPTS.hier_seperator)
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self.create_measurement_objects()
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self.recover_measurment_objects()
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else:
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@@ -1522,3 +1531,6 @@ class delay(simulation):
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self.stim.gen_pwl("CSB{0}".format(port), self.cycle_times, self.csb_values[port], self.period, self.slew, 0.05)
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if port in self.readwrite_ports:
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self.stim.gen_pwl("WEB{0}".format(port), self.cycle_times, self.web_values[port], self.period, self.slew, 0.05)
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if self.sram.num_wmasks:
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for bit in range(self.sram.num_wmasks):
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self.stim.gen_pwl("WMASK{0}_{1}".format(port, bit), self.cycle_times, self.wmask_values[port][bit], self.period, self.slew, 0.05)
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