mirror of https://github.com/VLSIDA/OpenRAM.git
Fix delays in ngspice as they are diff than hspice
This commit is contained in:
parent
b82aaa4201
commit
7fcce2633f
|
|
@ -47,16 +47,17 @@ class timing_sram_test(unittest.TestCase):
|
|||
d = delay.delay(s,tempspice)
|
||||
data = d.analyze(probe_address, probe_data)
|
||||
|
||||
print data
|
||||
if OPTS.tech_name == "freepdk45":
|
||||
self.assertTrue(isclose(data['delay1'],0.013649))
|
||||
self.assertTrue(isclose(data['delay0'],0.22893))
|
||||
self.assertTrue(isclose(data['min_period1'],0.078582763671875))
|
||||
self.assertTrue(isclose(data['min_period0'],0.25543212890625))
|
||||
elif OPTS.tech_name == "scn3me_subm":
|
||||
self.assertTrue(isclose(data['delay1'],1.66442871094)) # diff than hspice
|
||||
self.assertTrue(isclose(data['delay0'],2.2635000000000005))
|
||||
self.assertTrue(isclose(data['min_period1'],1.53564453125))
|
||||
self.assertTrue(isclose(data['min_period0'],2.998046875))
|
||||
self.assertTrue(isclose(data['delay1'],1.617351)) # diff than hspice
|
||||
self.assertTrue(isclose(data['delay0'],0.2980481)) # diff than hspice
|
||||
self.assertTrue(isclose(data['min_period1'],1.6650390625)) # diff than hspice
|
||||
self.assertTrue(isclose(data['min_period0'],1.25244140625)) # diff than hspice
|
||||
else:
|
||||
self.assertTrue(False) # other techs fail
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue