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route glitch3 to inverter on wen row

This commit is contained in:
samuelkcrow 2022-07-16 09:56:09 -07:00
parent 231dca5b51
commit 7f52e63aca
1 changed files with 3 additions and 0 deletions
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3
compiler/modules/control_logic_delay.py
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@ -656,6 +656,9 @@ class control_logic_delay(design.design):
self.row_end_inst.append(self.w_en_gate_inst) self.row_end_inst.append(self.w_en_gate_inst)
def route_wen(self): # w_en comes from a 3and but one of the inputs needs to be inverted def route_wen(self): # w_en comes from a 3and but one of the inputs needs to be inverted
glitch3_map = zip(["A"], ["glitch3"])
self.connect_vertical_bus(glitch3_map, self.glitch3_bar_inv_inst, self.input_bus)
out_pin = self.glitch3_bar_inv_inst.get_pin("Z") out_pin = self.glitch3_bar_inv_inst.get_pin("Z")
out_pos = out_pin.center() out_pos = out_pin.center()
in_pin = self.w_en_gate_inst.get_pin("C") in_pin = self.w_en_gate_inst.get_pin("C")