mirror of https://github.com/VLSIDA/OpenRAM.git
Add some vertical/horizontal pins for sky130 only
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8979612cca
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7e7670581c
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@ -449,12 +449,19 @@ class layout():
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bins[x] = [(inst,pin)]
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bins[x] = [(inst,pin)]
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for x, v in bins.items():
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for x, v in bins.items():
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# Not enough to route a pin
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# Not enough to route a pin, so just copy them
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if len(v) < 2:
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if len(v) < 2:
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debug.warning("Copying pins instead of connecting with pin.")
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for inst,pin in v:
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self.add_layout_pin(pin.name,
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pin.layer,
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pin.ll(),
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pin.width(),
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pin.height())
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continue
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continue
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bot_y = min([inst.by() for (inst,pin) in v])
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bot_y = min([pin.by() for (inst,pin) in v])
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top_y = max([inst.uy() for (inst,pin) in v])
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top_y = max([pin.uy() for (inst,pin) in v])
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last_via = None
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last_via = None
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for inst,pin in v:
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for inst,pin in v:
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@ -477,16 +484,21 @@ class layout():
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top_pos = vector(x, top_y)
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top_pos = vector(x, top_y)
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bot_pos = vector(x, bot_y)
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bot_pos = vector(x, bot_y)
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rect = self.add_layout_pin_rect_center(text=name,
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# top_rect = self.add_layout_pin_rect_center(text=name,
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layer=pin_layer,
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# layer=pin_layer,
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offset=top_pos)
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# offset=top_pos)
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# self.add_layout_pin_rect_center(text=name,
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#bot_rect = self.add_layout_pin_rect_center(text=name,
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# layer=pin_layer,
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# layer=pin_layer,
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# offset=bot_pos)
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# offset=bot_pos)
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self.add_segment_center(layer=pin_layer,
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# self.add_segment_center(layer=pin_layer,
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start=vector(rect.cx(), bot_pos.y),
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# start=vector(top_rect.cx(), bot_pos.y),
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end=rect.bc(),
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# end=top_rect.bc(),
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width=via_width)
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# width=via_width)
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self.add_layout_pin_segment_center(text=name,
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layer=pin_layer,
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start=top_pos,
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end=bot_pos,
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width=via_width)
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@ -514,12 +526,18 @@ class layout():
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# Filter the small bins
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# Filter the small bins
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for y, v in bins.items():
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for y, v in bins.items():
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# Not enough to route a pin
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if len(v) < 2:
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if len(v) < 2:
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debug.warning("Copying pins instead of connecting with pin.")
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for inst,pin in v:
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self.add_layout_pin(pin.name,
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pin.layer,
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pin.ll(),
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pin.width(),
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pin.height())
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continue
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continue
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left_x = min([inst.lx() for (inst,pin) in v])
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left_x = min([pin.lx() for (inst,pin) in v])
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right_x = max([inst.rx() for (inst,pin) in v])
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right_x = max([pin.rx() for (inst,pin) in v])
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last_via = None
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last_via = None
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for inst,pin in v:
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for inst,pin in v:
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@ -543,19 +561,25 @@ class layout():
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left_pos = vector(left_x, y)
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left_pos = vector(left_x, y)
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right_pos = vector(right_x, y)
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right_pos = vector(right_x, y)
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rect = self.add_layout_pin_rect_center(text=name,
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# left_rect = self.add_layout_pin_rect_center(text=name,
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layer=pin_layer,
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# layer=pin_layer,
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offset=left_pos)
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# offset=left_pos)
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# self.add_layout_pin_rect_center(text=name,
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#right_rect = self.add_layout_pin_rect_center(text=name,
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# layer=pin_layer,
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# layer=pin_layer,
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# offset=right_pos)
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# offset=right_pos)
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# This is made to not overlap with the pin above
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# This is made to not overlap with the pin above
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# so that the power router will only select a small pin.
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# so that the power router will only select a small pin.
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# Otherwise it adds big blockages over the rails.
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# Otherwise it adds big blockages over the rails.
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self.add_segment_center(layer=pin_layer,
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# self.add_segment_center(layer=pin_layer,
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start=rect.rc(),
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# start=left_rect.rc(),
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end=vector(right_pos.x, rect.cy()),
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# end=vector(right_pos.x, left_rect.cy()),
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width=via_height)
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# width=via_height)
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self.add_layout_pin_segment_center(text=name,
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layer=pin_layer,
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start=left_pos,
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end=right_pos,
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width=via_height)
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def add_layout_pin_segment_center(self, text, layer, start, end, width=None):
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def add_layout_pin_segment_center(self, text, layer, start, end, width=None):
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@ -596,7 +596,7 @@ class hierarchical_decoder(design.design):
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"""
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"""
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# This is an experiment with power rails
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# This is an experiment with power rails
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if OPTS.experimental_power:
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if OPTS.tech_name=="sky130" or OPTS.experimental_power:
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if layer_props.hierarchical_decoder.vertical_supply:
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if layer_props.hierarchical_decoder.vertical_supply:
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pre_insts = self.pre2x4_inst + self.pre3x8_inst + self.pre4x16_inst
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pre_insts = self.pre2x4_inst + self.pre3x8_inst + self.pre4x16_inst
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self.route_vertical_pins("vdd", insts=pre_insts, yside="by")
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self.route_vertical_pins("vdd", insts=pre_insts, yside="by")
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@ -95,7 +95,7 @@ class precharge_array(design.design):
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self.copy_layout_pin(inst, "br", "br_{0}".format(i))
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self.copy_layout_pin(inst, "br", "br_{0}".format(i))
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def route_supplies(self):
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def route_supplies(self):
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if OPTS.experimental_power:
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if OPTS.tech_name=="sky130" or OPTS.experimental_power:
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self.route_horizontal_pins("vdd")
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self.route_horizontal_pins("vdd")
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else:
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else:
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for inst in self.local_insts:
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for inst in self.local_insts:
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@ -458,27 +458,14 @@ class replica_bitcell_array(bitcell_base_array):
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width=pin.width(),
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width=pin.width(),
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height=self.height)
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height=self.height)
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# vdd/gnd are only connected in the perimeter cells
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if OPTS.tech_name=="sky130" or OPTS.experimental_power:
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# replica column should only have a vdd/gnd in the dummy cell on top/bottom
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self.route_vertical_pins(name="gnd", insts=self.replica_col_insts)
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supply_insts = self.dummy_col_insts + self.dummy_row_insts
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self.route_horizontal_pins(name="vdd", insts=self.dummy_row_insts)
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if OPTS.experimental_power:
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for pin_name in self.supplies:
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#self.route_vertical_pins(name=pin_name, insts=supply_insts)
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self.route_horizontal_pins(name=pin_name, insts=supply_insts)
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#self.route_vertical_pins(name=pin_name, insts=self.replica_col_insts)
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#self.route_horizontal_pins(name=pin_name, insts=self.replica_col_insts)
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for inst in supply_insts:
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pin_list = inst.get_pins(pin_name)
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for pin in pin_list:
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self.copy_power_pin(pin)
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for inst in self.replica_col_insts:
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if inst:
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self.copy_layout_pin(inst, pin_name)
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else:
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else:
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# vdd/gnd are only connected in the perimeter cells
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# replica column should only have a vdd/gnd in the dummy cell on top/bottom
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supply_insts = self.dummy_col_insts + self.dummy_row_insts
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for pin_name in self.supplies:
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for pin_name in self.supplies:
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for inst in supply_insts:
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for inst in supply_insts:
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pin_list = inst.get_pins(pin_name)
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pin_list = inst.get_pins(pin_name)
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