Add code for isdiff to output diff in tests when files mismatch.

compiler/TODO

@@ -37,3 +37,4 @@ Make lib file have delay relative to negedge for DATA. Must update
 timing code too.
 
 Convert characterizer into a Python package
+

compiler/tests/23_lib_sram_test.py

@@ -4,7 +4,7 @@ Check the .lib file for an SRAM
 """
 
 import unittest
-from testutils import header
+from testutils import header,isdiff
 import sys,os
 sys.path.append(os.path.join(sys.path[0],".."))
 import globals
@@ -24,7 +24,6 @@ class lib_test(unittest.TestCase):
 
         import sram
         import lib
-        import filecmp
 
         debug.info(1, "Testing timing for sample 2 bit, 16 words SRAM with 1 bank")
         s = sram.sram(word_size=2,
@@ -44,7 +43,7 @@ class lib_test(unittest.TestCase):
         
         # let's diff the result with a golden model
         golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)),filename)
-        self.assertEqual(filecmp.cmp(libname,golden),True)
+        self.assertEqual(isdiff(libname,golden),True)
 
         os.system("rm {0}".format(libname))
 

compiler/tests/24_lef_sram_test.py

@@ -4,7 +4,7 @@ Check the LEF file for an SRMA
 """
 
 import unittest
-from testutils import header
+from testutils import header,isdiff
 import sys,os
 sys.path.append(os.path.join(sys.path[0],".."))
 import globals
@@ -23,7 +23,6 @@ class lef_test(unittest.TestCase):
 
         import sram
         import lef
-        import filecmp
 
         debug.info(1, "Testing LEF for sample 2 bit, 16 words SRAM with 1 bank")
         s = sram.sram(word_size=2,
@@ -43,7 +42,7 @@ class lef_test(unittest.TestCase):
 
         # let's diff the result with a golden model
         golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)),leffile)
-        self.assertEqual(filecmp.cmp(lefname,golden),True)
+        self.assertEqual(isdiff(lefname,golden),True)
 
         os.system("rm {0}".format(gdsname))
         os.system("rm {0}".format(lefname))

compiler/tests/25_verilog_sram_test.py

@@ -4,7 +4,7 @@ Check the  .v file for an SRAM
 """
 
 import unittest
-from testutils import header
+from testutils import header,isdiff
 import sys,os
 sys.path.append(os.path.join(sys.path[0],".."))
 import globals
@@ -23,7 +23,6 @@ class verilog_test(unittest.TestCase):
 
         import sram
         import verilog
-        import filecmp
 
         debug.info(1, "Testing Verilog for sample 2 bit, 16 words SRAM with 1 bank")
         s = sram.sram(word_size=2,
@@ -41,7 +40,7 @@ class verilog_test(unittest.TestCase):
 
         # let's diff the result with a golden model
         golden = "{0}/golden/{1}".format(os.path.dirname(os.path.realpath(__file__)),vfile)
-        self.assertEqual(filecmp.cmp(vname,golden),True)
+        self.assertEqual(isdiff(vname,golden),True)
 
         os.system("rm {0}".format(vname))
 

compiler/tests/testutils.py

@@ -1,7 +1,7 @@
 
 
 def isclose(value1,value2,error_tolerance=1e-2):
-    """ This is used to compare relative values.. """
+    """ This is used to compare relative values. """
     import debug
     relative_diff = abs(value1 - value2) / max(value1,value2)
     check = relative_diff <= error_tolerance
@@ -11,6 +11,24 @@ def isclose(value1,value2,error_tolerance=1e-2):
         debug.info(2,"CLOSE {0} {1} relative diff={2}".format(value1,value2,relative_diff))
     return (check)
 
+def isdiff(file1,file2):
+    """ This is used to compare two files and display the diff if they are different.. """
+    import debug
+    import filecmp
+    import difflib
+    check = filecmp.cmp(libname,golden)
+    if not check:
+        debug.info(2,"MISMATCH {0} {1}".format(file1,file2))
+        f1 = open(file1,"r")
+        s1 = f1.readlines()
+        f2 = open(file2,"r")
+        s2 = f2.readlines()
+        for line in unified_diff(s1, s2):
+            debug.error(line)   
+    else:
+        debug.info(2,"MATCH {0} {1}".format(file1,file2))
+    return (check)
+
 def header(str, tec):
     tst = "Running Test for:"
     print "\n"