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Some techs don't need m1 power pins

This commit is contained in:
Matt Guthaus 2018-11-29 18:47:38 -08:00
parent 0af4263edb
commit 7e054a51e2
2 changed files with 6 additions and 5 deletions
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9
compiler/base/hierarchy_layout.py
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@ -926,13 +926,14 @@ class layout(lef.lef):
def add_power_pin(self, name, loc, rotate=90): def add_power_pin(self, name, loc, rotate=90, m1_too=True):
""" """
Add a single power pin from M3 down to M1 at the given center location Add a single power pin from M3 down to M1 at the given center location
""" """
self.add_via_center(layers=("metal1", "via1", "metal2"), if m1_too:
offset=loc, self.add_via_center(layers=("metal1", "via1", "metal2"),
rotate=float(rotate)) offset=loc,
rotate=float(rotate))
via=self.add_via_center(layers=("metal2", "via2", "metal3"), via=self.add_via_center(layers=("metal2", "via2", "metal3"),
offset=loc, offset=loc,
rotate=float(rotate)) rotate=float(rotate))

2
compiler/modules/bitcell_array.py
View File

@ -138,7 +138,7 @@ class bitcell_array(design.design):
inst = self.cell_inst[row,col] inst = self.cell_inst[row,col]
for pin_name in ["vdd", "gnd"]: for pin_name in ["vdd", "gnd"]:
for pin in inst.get_pins(pin_name): for pin in inst.get_pins(pin_name):
self.add_power_pin(pin_name, pin.center(), 90) self.add_power_pin(pin_name, pin.center(), 0, pin.layer=="metal1")
def analytical_delay(self, slew, load=0): def analytical_delay(self, slew, load=0):
from tech import drc from tech import drc