mirror of https://github.com/VLSIDA/OpenRAM.git
Only output wmask to lib file in w or rw ports.
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@ -136,14 +136,14 @@ class lib:
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# set the read and write port as inputs.
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# set the read and write port as inputs.
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self.write_data_bus(port)
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self.write_data_bus(port)
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self.write_addr_bus(port)
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self.write_addr_bus(port)
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if self.sram.write_size:
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if self.sram.write_size and port in self.write_ports:
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self.write_wmask_bus(port)
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self.write_wmask_bus(port)
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self.write_control_pins(port) #need to split this into sram and port control signals
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# need to split this into sram and port control signals
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self.write_control_pins(port)
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self.write_clk_timing_power(port)
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self.write_clk_timing_power(port)
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self.write_footer()
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self.write_footer()
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def write_footer(self):
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def write_footer(self):
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""" Write the footer """
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""" Write the footer """
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self.lib.write(" }\n") #Closing brace for the cell
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self.lib.write(" }\n") #Closing brace for the cell
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