Don't make dummy bitlines pins for simplicity

compiler/modules/dummy_array.py

@@ -53,13 +53,60 @@ class dummy_array(bitcell_base_array):
                                                        mod=self.dummy_cell)
                 self.connect_inst(self.get_bitcell_pins(row, col))
 
+    def add_pins(self):
+        # bitline pins are not added because they are floating
+        for wl_name in self.get_wordline_names():
+            self.add_pin(wl_name, "INPUT")
+        self.add_pin("vdd", "POWER")
+        self.add_pin("gnd", "GROUND")
+                
+    def add_layout_pins(self):
+        """ Add the layout pins """
+
+        # Add the bitline metal, but not as pins since they are going to just be floating
+        # For some reason, LVS has an issue if we don't add this metal
+        bitline_names = self.cell.get_all_bitline_names()
+        for col in range(self.column_size):
+            for port in self.all_ports:
+                bl_pin = self.cell_inst[0, col].get_pin(bitline_names[2 * port])
+                self.add_rect(layer=bl_pin.layer,
+                              offset=bl_pin.ll().scale(1, 0),
+                              width=bl_pin.width(),
+                              height=self.height)
+                br_pin = self.cell_inst[0, col].get_pin(bitline_names[2 * port + 1])
+                self.add_rect(layer=br_pin.layer,
+                              offset=br_pin.ll().scale(1, 0),
+                              width=br_pin.width(),
+                              height=self.height)
+        
+        wl_names = self.cell.get_all_wl_names()
+        for row in range(self.row_size):
+            for port in self.all_ports:
+                wl_pin = self.cell_inst[row, 0].get_pin(wl_names[port])
+                self.add_layout_pin(text="wl_{0}_{1}".format(port, row),
+                                    layer=wl_pin.layer,
+                                    offset=wl_pin.ll().scale(0, 1),
+                                    width=self.width,
+                                    height=wl_pin.height())
+
+        # Copy a vdd/gnd layout pin from every cell
+        for row in range(self.row_size):
+            for col in range(self.column_size):
+                inst = self.cell_inst[row, col]
+                for pin_name in ["vdd", "gnd"]:
+                    self.copy_layout_pin(inst, pin_name)
+
     def input_load(self):
         wl_wire = self.gen_wl_wire()
         return wl_wire.return_input_cap()
 
     def get_wordline_cin(self):
-        """Get the relative input capacitance from the wordline connections in all the bitcell"""
-        # A single wordline is connected to all the bitcells in a single row meaning the capacitance depends on the # of columns
+        """ 
+        Get the relative input capacitance from the 
+        wordline connections in all the bitcell 
+        """
+        # A single wordline is connected to all the bitcells
+        # in a single row meaning the capacitance depends on the # of columns
         bitcell_wl_cin = self.cell.get_wl_cin()
         total_cin = bitcell_wl_cin * self.column_size
         return total_cin