Altered web to only be generated for rw ports.

compiler/characterizer/delay.py

@@ -227,8 +227,8 @@ class delay():
         self.sf.write("\n* Generation of control signals\n")
         for port in range(self.total_port_num):
             self.stim.gen_constant(sig_name="CSB{0}".format(port), v_val=self.vdd_voltage)
-        for port in self.write_ports:
+            if port in self.write_ports and port in self.read_ports:
-            self.stim.gen_constant(sig_name="WEB{0}".format(port), v_val=self.vdd_voltage)
+                self.stim.gen_constant(sig_name="WEB{0}".format(port), v_val=self.vdd_voltage)
 
         self.sf.write("\n* Generation of global clock signal\n")
         for port in range(self.total_port_num):
@@ -846,7 +846,7 @@ class delay():
         #Append the values depending on the type of port
         self.csb_values[port].append(csb_val)
         #If port is in both lists, add rw control signal. Condition indicates its a RW port.
-        if port in self.write_ports:
+        if port in self.write_ports and port in self.read_ports:
             self.web_values[port].append(web_val)
 
     def add_comment(self, port, comment):
@@ -1045,9 +1045,9 @@ class delay():
         """ Generates the control signals """
         for port in range(self.total_port_num):
             self.stim.gen_pwl("CSB{0}".format(port), self.cycle_times, self.csb_values[port], self.period, self.slew, 0.05)
+            if port in self.read_ports and port in self.write_ports:
+                self.stim.gen_pwl("WEB{0}".format(port), self.cycle_times, self.web_values[port], self.period, self.slew, 0.05)
         
-        for port in self.write_ports:
-            self.stim.gen_pwl("WEB{0}".format(port), self.cycle_times, self.web_values[port], self.period, self.slew, 0.05)
             
     def get_empty_measure_data_dict(self):
         """Make a dict of lists for each type of delay and power measurement to append results to"""

compiler/characterizer/stimuli.py

@@ -72,8 +72,9 @@ class stimuli():
         #Control signals not finalized.
         for port in range(total_port_num):
             pin_names.append("CSB{0}".format(port))
-        for port in write_ports:
+        for port in range(total_port_num):
-            pin_names.append("WEB{0}".format(port))
+            if port in read_ports and port in write_ports:
+                pin_names.append("WEB{0}".format(port))
             
         for port in range(total_port_num):
             pin_names.append("{0}{1}".format(tech.spice["clk"], port))

compiler/example_config_freepdk45.py

@@ -11,6 +11,9 @@ output_path = "temp"
 output_name = "sram_{0}_{1}_{2}_{3}".format(word_size,num_words,num_banks,tech_name)
 
 #Setting for multiport
-netlist_only = True
+# netlist_only = True
-bitcell = "pbitcell"
+# bitcell = "pbitcell"
-replica_bitcell="replica_pbitcell"
+# replica_bitcell="replica_pbitcell"
+# num_rw_ports = 1
+# num_r_ports = 0
+# num_w_ports = 1

compiler/example_config_scn4m_subm.py

@@ -11,9 +11,9 @@ output_path = "temp"
 output_name = "sram_{0}_{1}_{2}_{3}".format(word_size,num_words,num_banks,tech_name)
 
 #Setting for multiport
-#netlist_only = True
+# netlist_only = True
-#bitcell = "pbitcell"
+# bitcell = "pbitcell"
-#replica_bitcell="replica_pbitcell"
+# replica_bitcell="replica_pbitcell"
-#num_rw_ports = 1
+# num_rw_ports = 1
-#num_r_ports = 1
+# num_r_ports = 1
-#num_w_ports = 0
+# num_w_ports = 0

compiler/tests/22_hspice_psram_func_test.py

@@ -11,7 +11,7 @@ import globals
 from globals import OPTS
 import debug
 
-@unittest.skip("SKIPPING 22_psram_func_test")
+#@unittest.skip("SKIPPING 22_psram_func_test")
 class psram_func_test(openram_test):
 
     def runTest(self):

compiler/tests/22_hspice_sram_func_test.py

@@ -11,7 +11,7 @@ import globals
 from globals import OPTS
 import debug
 
-@unittest.skip("SKIPPING 22_sram_func_test")
+#@unittest.skip("SKIPPING 22_sram_func_test")
 class sram_func_test(openram_test):
 
     def runTest(self):