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PEP8 formatting

This commit is contained in:
mrg 2020-04-20 14:45:18 -07:00
parent 69d0e5e372
commit 7995451cbb
1 changed files with 26 additions and 37 deletions
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63
compiler/modules/single_level_column_mux_array.py
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@ -5,17 +5,14 @@
# (acting for and on behalf of Oklahoma State University) # (acting for and on behalf of Oklahoma State University)
# All rights reserved. # All rights reserved.
# #
from math import log
import design import design
import contact
from tech import drc
import debug import debug
import math
from vector import vector from vector import vector
from sram_factory import factory from sram_factory import factory
from globals import OPTS from globals import OPTS
import logical_effort import logical_effort
class single_level_column_mux_array(design.design): class single_level_column_mux_array(design.design):
""" """
Dynamically generated column mux array. Dynamically generated column mux array.
@ -56,7 +53,7 @@ class single_level_column_mux_array(design.design):
self.add_routing() self.add_routing()
# Find the highest shapes to determine height before adding well # Find the highest shapes to determine height before adding well
highest = self.find_highest_coords() highest = self.find_highest_coords()
self.height = highest.y self.height = highest.y
self.add_layout_pins() self.add_layout_pins()
self.add_enclosure(self.mux_inst, "pwell") self.add_enclosure(self.mux_inst, "pwell")
@ -74,22 +71,18 @@ class single_level_column_mux_array(design.design):
self.add_pin("br_out_{}".format(i)) self.add_pin("br_out_{}".format(i))
self.add_pin("gnd") self.add_pin("gnd")
def add_modules(self): def add_modules(self):
self.mux = factory.create(module_type="single_level_column_mux", self.mux = factory.create(module_type="single_level_column_mux",
bitcell_bl=self.bitcell_bl, bitcell_bl=self.bitcell_bl,
bitcell_br=self.bitcell_br) bitcell_br=self.bitcell_br)
self.add_mod(self.mux) self.add_mod(self.mux)
def setup_layout_constants(self): def setup_layout_constants(self):
self.column_addr_size = num_of_inputs = int(self.words_per_row / 2) self.column_addr_size = int(self.words_per_row / 2)
self.width = self.columns * self.mux.width self.width = self.columns * self.mux.width
# one set of metal1 routes for select signals and a pair to interconnect the mux outputs bl/br # one set of metal1 routes for select signals and a pair to interconnect the mux outputs bl/br
# one extra route pitch is to space from the sense amp # one extra route pitch is to space from the sense amp
self.route_height = (self.words_per_row + 3)*self.m1_pitch self.route_height = (self.words_per_row + 3) * self.m1_pitch
def create_array(self): def create_array(self):
self.mux_inst = [] self.mux_inst = []
@ -101,8 +94,8 @@ class single_level_column_mux_array(design.design):
self.connect_inst(["bl_{}".format(col_num), self.connect_inst(["bl_{}".format(col_num),
"br_{}".format(col_num), "br_{}".format(col_num),
"bl_out_{}".format(int(col_num/self.words_per_row)), "bl_out_{}".format(int(col_num / self.words_per_row)),
"br_out_{}".format(int(col_num/self.words_per_row)), "br_out_{}".format(int(col_num / self.words_per_row)),
"sel_{}".format(col_num % self.words_per_row), "sel_{}".format(col_num % self.words_per_row),
"gnd"]) "gnd"])
@ -117,11 +110,9 @@ class single_level_column_mux_array(design.design):
else: else:
mirror = "" mirror = ""
name = "XMUX{0}".format(col_num)
offset = vector(xoffset, self.route_height) offset = vector(xoffset, self.route_height)
self.mux_inst[col_num].place(offset=offset, mirror=mirror) self.mux_inst[col_num].place(offset=offset, mirror=mirror)
def add_layout_pins(self): def add_layout_pins(self):
""" Add the pins after we determine the height. """ """ Add the pins after we determine the height. """
# For every column, add a pass gate # For every column, add a pass gate
@ -131,18 +122,17 @@ class single_level_column_mux_array(design.design):
self.add_layout_pin(text="bl_{}".format(col_num), self.add_layout_pin(text="bl_{}".format(col_num),
layer="m2", layer="m2",
offset=offset, offset=offset,
height=self.height-offset.y) height=self.height - offset.y)
offset = mux_inst.get_pin("br").ll() offset = mux_inst.get_pin("br").ll()
self.add_layout_pin(text="br_{}".format(col_num), self.add_layout_pin(text="br_{}".format(col_num),
layer="m2", layer="m2",
offset=offset, offset=offset,
height=self.height-offset.y) height=self.height - offset.y)
for inst in self.mux_inst: for inst in self.mux_inst:
self.copy_layout_pin(inst, "gnd") self.copy_layout_pin(inst, "gnd")
def add_routing(self): def add_routing(self):
self.add_horizontal_input_rail() self.add_horizontal_input_rail()
self.add_vertical_poly_rail() self.add_vertical_poly_rail()
@ -151,7 +141,7 @@ class single_level_column_mux_array(design.design):
def add_horizontal_input_rail(self): def add_horizontal_input_rail(self):
""" Create address input rails on M1 below the mux transistors """ """ Create address input rails on M1 below the mux transistors """
for j in range(self.words_per_row): for j in range(self.words_per_row):
offset = vector(0, self.route_height + (j-self.words_per_row)*self.m1_pitch) offset = vector(0, self.route_height + (j - self.words_per_row) * self.m1_pitch)
self.add_layout_pin(text="sel_{}".format(j), self.add_layout_pin(text="sel_{}".format(j),
layer="m1", layer="m1",
offset=offset, offset=offset,
@ -167,9 +157,10 @@ class single_level_column_mux_array(design.design):
# Add the column x offset to find the right select bit # Add the column x offset to find the right select bit
gate_offset = self.mux_inst[col].get_pin("sel").bc() gate_offset = self.mux_inst[col].get_pin("sel").bc()
# height to connect the gate to the correct horizontal row # height to connect the gate to the correct horizontal row
sel_height = self.get_pin("sel_{}".format(sel_index)).by() # sel_height = self.get_pin("sel_{}".format(sel_index)).by()
# use the y offset from the sel pin and the x offset from the gate # use the y offset from the sel pin and the x offset from the gate
offset = vector(gate_offset.x,self.get_pin("sel_{}".format(sel_index)).cy()) offset = vector(gate_offset.x,
self.get_pin("sel_{}".format(sel_index)).cy())
# Add the poly contact with a shift to account for the rotation # Add the poly contact with a shift to account for the rotation
self.add_via_center(layers=("m1", "contact", "poly"), self.add_via_center(layers=("m1", "contact", "poly"),
offset=offset) offset=offset)
@ -182,11 +173,11 @@ class single_level_column_mux_array(design.design):
bl_offset = self.mux_inst[j].get_pin("bl_out").bc() bl_offset = self.mux_inst[j].get_pin("bl_out").bc()
br_offset = self.mux_inst[j].get_pin("br_out").bc() br_offset = self.mux_inst[j].get_pin("br_out").bc()
bl_out_offset = bl_offset - vector(0,(self.words_per_row+1)*self.m1_pitch) bl_out_offset = bl_offset - vector(0, (self.words_per_row + 1) * self.m1_pitch)
br_out_offset = br_offset - vector(0,(self.words_per_row+2)*self.m1_pitch) br_out_offset = br_offset - vector(0, (self.words_per_row + 2) * self.m1_pitch)
bl_out_offset_end = bl_out_offset + vector(0,self.route_height) bl_out_offset_end = bl_out_offset + vector(0, self.route_height)
br_out_offset_end = br_out_offset + vector(0,self.route_height) br_out_offset_end = br_out_offset + vector(0, self.route_height)
if cell_properties.bitcell.mirror.y and j % 2: if cell_properties.bitcell.mirror.y and j % 2:
tmp_bl_out_end = br_out_offset_end tmp_bl_out_end = br_out_offset_end
@ -208,21 +199,20 @@ class single_level_column_mux_array(design.design):
else: else:
dist = 0 dist = 0
self.add_path("m1", [bl_out_offset, bl_out_offset+vector(width+dist,0)]) self.add_path("m1", [bl_out_offset, bl_out_offset + vector(width + dist, 0)])
self.add_path("m1", [br_out_offset, br_out_offset+vector(width-dist,0)]) self.add_path("m1", [br_out_offset, br_out_offset + vector(width - dist, 0)])
# Extend the bitline output rails and gnd downward on the first bit of each n-way mux # Extend the bitline output rails and gnd downward on the first bit of each n-way mux
self.add_layout_pin_segment_center(text="bl_out_{}".format(int(j/self.words_per_row)), self.add_layout_pin_segment_center(text="bl_out_{}".format(int(j / self.words_per_row)),
layer="m2", layer="m2",
start=bl_out_offset, start=bl_out_offset,
end=tmp_bl_out_end) end=tmp_bl_out_end)
self.add_layout_pin_segment_center(text="br_out_{}".format(int(j/self.words_per_row)), self.add_layout_pin_segment_center(text="br_out_{}".format(int(j / self.words_per_row)),
layer="m2", layer="m2",
start=br_out_offset, start=br_out_offset,
end=tmp_br_out_end) end=tmp_br_out_end)
# This via is on the right of the wire
# This via is on the right of the wire
self.add_via_center(layers=self.m1_stack, self.add_via_center(layers=self.m1_stack,
offset=bl_out_offset) offset=bl_out_offset)
@ -231,20 +221,19 @@ class single_level_column_mux_array(design.design):
offset=br_out_offset) offset=br_out_offset)
else: else:
self.add_path("m2", [bl_out_offset, tmp_bl_out_end])
self.add_path("m2", [ bl_out_offset, tmp_bl_out_end]) self.add_path("m2", [br_out_offset, tmp_br_out_end])
self.add_path("m2", [ br_out_offset, tmp_br_out_end])
# This via is on the right of the wire # This via is on the right of the wire
self.add_via_center(layers=self.m1_stack, self.add_via_center(layers=self.m1_stack,
offset=bl_out_offset) offset=bl_out_offset)
# This via is on the left of the wire # This via is on the left of the wire
self.add_via_center(layers=self.m1_stack, self.add_via_center(layers=self.m1_stack,
offset=br_out_offset) offset=br_out_offset)
def get_drain_cin(self): def get_drain_cin(self):
"""Get the relative capacitance of the drain of the NMOS pass TX""" """Get the relative capacitance of the drain of the NMOS pass TX"""
from tech import parameter from tech import parameter
#Bitcell drain load being used to estimate mux NMOS drain load # Bitcell drain load being used to estimate mux NMOS drain load
drain_load = logical_effort.convert_farad_to_relative_c(parameter['bitcell_drain_cap']) drain_load = logical_effort.convert_farad_to_relative_c(parameter['bitcell_drain_cap'])
return drain_load return drain_load