mirror of https://github.com/VLSIDA/OpenRAM.git
PEP8 formatting
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@ -5,17 +5,14 @@
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# (acting for and on behalf of Oklahoma State University)
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# (acting for and on behalf of Oklahoma State University)
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# All rights reserved.
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# All rights reserved.
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#
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#
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from math import log
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import design
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import design
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import contact
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from tech import drc
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import debug
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import debug
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import math
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from vector import vector
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from vector import vector
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from sram_factory import factory
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from sram_factory import factory
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from globals import OPTS
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from globals import OPTS
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import logical_effort
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import logical_effort
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class single_level_column_mux_array(design.design):
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class single_level_column_mux_array(design.design):
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"""
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"""
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Dynamically generated column mux array.
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Dynamically generated column mux array.
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@ -74,23 +71,19 @@ class single_level_column_mux_array(design.design):
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self.add_pin("br_out_{}".format(i))
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self.add_pin("br_out_{}".format(i))
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self.add_pin("gnd")
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self.add_pin("gnd")
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def add_modules(self):
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def add_modules(self):
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self.mux = factory.create(module_type="single_level_column_mux",
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self.mux = factory.create(module_type="single_level_column_mux",
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bitcell_bl=self.bitcell_bl,
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bitcell_bl=self.bitcell_bl,
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bitcell_br=self.bitcell_br)
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bitcell_br=self.bitcell_br)
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self.add_mod(self.mux)
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self.add_mod(self.mux)
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def setup_layout_constants(self):
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def setup_layout_constants(self):
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self.column_addr_size = num_of_inputs = int(self.words_per_row / 2)
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self.column_addr_size = int(self.words_per_row / 2)
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self.width = self.columns * self.mux.width
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self.width = self.columns * self.mux.width
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# one set of metal1 routes for select signals and a pair to interconnect the mux outputs bl/br
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# one set of metal1 routes for select signals and a pair to interconnect the mux outputs bl/br
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# one extra route pitch is to space from the sense amp
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# one extra route pitch is to space from the sense amp
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self.route_height = (self.words_per_row + 3) * self.m1_pitch
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self.route_height = (self.words_per_row + 3) * self.m1_pitch
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def create_array(self):
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def create_array(self):
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self.mux_inst = []
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self.mux_inst = []
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# For every column, add a pass gate
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# For every column, add a pass gate
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@ -117,11 +110,9 @@ class single_level_column_mux_array(design.design):
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else:
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else:
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mirror = ""
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mirror = ""
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name = "XMUX{0}".format(col_num)
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offset = vector(xoffset, self.route_height)
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offset = vector(xoffset, self.route_height)
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self.mux_inst[col_num].place(offset=offset, mirror=mirror)
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self.mux_inst[col_num].place(offset=offset, mirror=mirror)
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def add_layout_pins(self):
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def add_layout_pins(self):
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""" Add the pins after we determine the height. """
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""" Add the pins after we determine the height. """
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# For every column, add a pass gate
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# For every column, add a pass gate
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@ -142,7 +133,6 @@ class single_level_column_mux_array(design.design):
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for inst in self.mux_inst:
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for inst in self.mux_inst:
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self.copy_layout_pin(inst, "gnd")
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self.copy_layout_pin(inst, "gnd")
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def add_routing(self):
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def add_routing(self):
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self.add_horizontal_input_rail()
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self.add_horizontal_input_rail()
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self.add_vertical_poly_rail()
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self.add_vertical_poly_rail()
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@ -167,9 +157,10 @@ class single_level_column_mux_array(design.design):
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# Add the column x offset to find the right select bit
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# Add the column x offset to find the right select bit
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gate_offset = self.mux_inst[col].get_pin("sel").bc()
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gate_offset = self.mux_inst[col].get_pin("sel").bc()
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# height to connect the gate to the correct horizontal row
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# height to connect the gate to the correct horizontal row
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sel_height = self.get_pin("sel_{}".format(sel_index)).by()
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# sel_height = self.get_pin("sel_{}".format(sel_index)).by()
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# use the y offset from the sel pin and the x offset from the gate
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# use the y offset from the sel pin and the x offset from the gate
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offset = vector(gate_offset.x,self.get_pin("sel_{}".format(sel_index)).cy())
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offset = vector(gate_offset.x,
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self.get_pin("sel_{}".format(sel_index)).cy())
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# Add the poly contact with a shift to account for the rotation
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# Add the poly contact with a shift to account for the rotation
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self.add_via_center(layers=("m1", "contact", "poly"),
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self.add_via_center(layers=("m1", "contact", "poly"),
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offset=offset)
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offset=offset)
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@ -221,7 +212,6 @@ class single_level_column_mux_array(design.design):
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start=br_out_offset,
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start=br_out_offset,
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end=tmp_br_out_end)
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end=tmp_br_out_end)
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# This via is on the right of the wire
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# This via is on the right of the wire
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self.add_via_center(layers=self.m1_stack,
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self.add_via_center(layers=self.m1_stack,
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offset=bl_out_offset)
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offset=bl_out_offset)
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@ -231,7 +221,6 @@ class single_level_column_mux_array(design.design):
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offset=br_out_offset)
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offset=br_out_offset)
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else:
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else:
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self.add_path("m2", [bl_out_offset, tmp_bl_out_end])
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self.add_path("m2", [bl_out_offset, tmp_bl_out_end])
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self.add_path("m2", [br_out_offset, tmp_br_out_end])
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self.add_path("m2", [br_out_offset, tmp_br_out_end])
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