luke/OpenRAM
1
0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-09-04 00:40:09 +02:00
Code Issues Packages Projects Releases Wiki Activity

Cleanup and rename vias.

Browse Source
This commit is contained in:
mrg
2020-01-30 01:45:33 +00:00
parent 3147b99ce0
commit 79391b84da
22 changed files with 106 additions and 87 deletions
Download Patch File Download Diff File Expand all files Collapse all files
compiler/modules/multibank.py
+2 -2
View File
@@ -810,7 +810,7 @@ class multibank(design.design):
self.add_wire(("m3","via2","m2"),[in_pin, rail_pos, rail_pos - vector(0,self.m2_pitch)])
# Bring it up to M2 for M2/M3 routing
self.add_via(layers=self.m1_stack,
offset=in_pin + contact.m1m2.offset,
offset=in_pin + contact.m1_via.offset,
rotate=90)
self.add_via(layers=self.m2_stack,
offset=in_pin + self.m2m3_via_offset,
@@ -823,7 +823,7 @@ class multibank(design.design):
rail_pos = vector(self.rail_1_x_offsets[rail], in_pin.y)
self.add_wire(("m3","via2","m2"),[in_pin, rail_pos, rail_pos - vector(0,self.m2_pitch)])
self.add_via(layers=self.m1_stack,
offset=in_pin + contact.m1m2.offset,
offset=in_pin + contact.m1_via.offset,
rotate=90)
self.add_via(layers=self.m2_stack,
offset=in_pin + self.m2m3_via_offset,