Cleanup and rename vias.

compiler/modules/bank_select.py

@@ -256,7 +256,7 @@ class bank_select(design.design):
             
             
             # Connect the logic B input to bank_sel/bank_sel_bar
-            logic_pos = logic_inst.get_pin("B").lc() - vector(0.5*contact.m1m2.height,0)
+            logic_pos = logic_inst.get_pin("B").lc() - vector(0.5*contact.m1_via.height,0)
             input_pos = vector(xoffset_bank_signal, logic_pos.y)
             self.add_path("m2",[logic_pos, input_pos])
             self.add_via_center(layers=self.m1_stack,

compiler/modules/bitcell_array.py

@@ -5,14 +5,11 @@
 # (acting for and on behalf of Oklahoma State University)
 # All rights reserved.
 #
-import debug
-import design
-from base_array import bitcell_base_array
+from bitcell_base_array import bitcell_base_array
 from tech import drc, spice
-from vector import vector
 from globals import OPTS
 from sram_factory import factory
-import logical_effort
+
 
 class bitcell_array(bitcell_base_array):
     """
@@ -29,7 +26,7 @@ class bitcell_array(bitcell_base_array):
 
         # We don't offset this because we need to align
         # the replica bitcell in the control logic
-        #self.offset_all_coordinates()
+        # self.offset_all_coordinates()
         
         
     def create_netlist(self):
@@ -48,13 +45,11 @@ class bitcell_array(bitcell_base_array):
         
         self.DRC_LVS()
 
-
     def add_modules(self):
         """ Add the modules used in this design """
         self.cell = factory.create(module_type="bitcell")
         self.add_mod(self.cell)
 
-    
     def create_instances(self):
         """ Create the module instances used in this design """
         self.cell_inst = {}
@@ -65,7 +60,6 @@ class bitcell_array(bitcell_base_array):
                                                       mod=self.cell)
                 self.connect_inst(self.get_bitcell_pins(col, row))
         
-
     def analytical_power(self, corner, load):
         """Power of Bitcell array and bitline in nW."""
         from tech import drc, parameter
@@ -77,10 +71,10 @@ class bitcell_array(bitcell_base_array):
         freq = spice["default_event_frequency"]
         bitline_dynamic = self.calc_dynamic_power(corner, cell_load, freq, swing=bl_swing)
         
-        #Calculate the bitcell power which currently only includes leakage 
+        # Calculate the bitcell power which currently only includes leakage 
         cell_power = self.cell.analytical_power(corner, load)
         
-        #Leakage power grows with entire array and bitlines.
+        # Leakage power grows with entire array and bitlines.
         total_power = self.return_power(cell_power.dynamic + bitline_dynamic * self.column_size,
                                         cell_power.leakage * self.column_size * self.row_size)
         return total_power

compiler/modules/custom_cell_properties.py

@@ -1,28 +0,0 @@
-# See LICENSE for licensing information.
-#
-# Copyright (c) 2016-2020 Regents of the University of California and The Board
-# of Regents for the Oklahoma Agricultural and Mechanical College
-# (acting for and on behalf of Oklahoma State University)
-# All rights reserved.
-#
-
-class _MirrorAxis:
-    def __init__(self, x, y):
-        self.x = x
-        self.y = y
-
-class _Bitcell:
-    def __init__(self, mirror):
-        self.mirror = mirror
-
-class CellProperties():
-    """
-    TODO
-    """
-    def __init__(self):
-        self.names = {}
-        self._bitcell = _Bitcell(_MirrorAxis(True, False))
-
-    @property
-    def bitcell(self):
-        return self._bitcell

compiler/modules/hierarchical_predecode.py

@@ -178,7 +178,7 @@ class hierarchical_predecode(design.design):
             # route one signal next to each vdd/gnd rail since this is
             # typically where the p/n devices are and there are no
             # pins in the nand gates. 
-            y_offset = (num+self.number_of_inputs) * self.inv.height + contact.m1m2.width + self.m1_space
+            y_offset = (num+self.number_of_inputs) * self.inv.height + contact.m1_via.width + self.m1_space
             in_pin = "in_{}".format(num)            
             a_pin = "A_{}".format(num)
             in_pos = vector(self.input_rails[in_pin].x,y_offset)

compiler/modules/module_type.py

@@ -6,7 +6,7 @@
 # All rights reserved.
 #
 
-class ModuleType():
+class module_type():
     """
     This is a class that maps cell names to python classes implementing them.
     """

compiler/modules/multibank.py

@@ -810,7 +810,7 @@ class multibank(design.design):
         self.add_wire(("m3","via2","m2"),[in_pin, rail_pos, rail_pos - vector(0,self.m2_pitch)])
         # Bring it up to M2 for M2/M3 routing
         self.add_via(layers=self.m1_stack,
-                     offset=in_pin + contact.m1m2.offset,
+                     offset=in_pin + contact.m1_via.offset,
                      rotate=90)
         self.add_via(layers=self.m2_stack,
                      offset=in_pin + self.m2m3_via_offset,
@@ -823,7 +823,7 @@ class multibank(design.design):
         rail_pos = vector(self.rail_1_x_offsets[rail], in_pin.y)
         self.add_wire(("m3","via2","m2"),[in_pin, rail_pos, rail_pos - vector(0,self.m2_pitch)])
         self.add_via(layers=self.m1_stack,
-                     offset=in_pin + contact.m1m2.offset,
+                     offset=in_pin + contact.m1_via.offset,
                      rotate=90)
         self.add_via(layers=self.m2_stack,
                      offset=in_pin + self.m2m3_via_offset,

compiler/modules/wordline_driver.py

@@ -177,7 +177,7 @@ class wordline_driver(design.design):
             up_or_down = self.m2_space if row % 2 else -self.m2_space
             input_offset = vector(0, b_pos.y + up_or_down)
             base_offset = vector(clk_offset.x, input_offset.y)
-            contact_offset = vector(0.5 * self.m2_width + self.m2_space + 0.5 * contact.m1m2.width, 0) 
+            contact_offset = vector(0.5 * self.m2_width + self.m2_space + 0.5 * contact.m1_via.width, 0) 
             mid_via_offset = base_offset + contact_offset
 
             # must under the clk line in M1
@@ -191,7 +191,7 @@ class wordline_driver(design.design):
 
             # now connect to the nand2 B
             self.add_path("m2", [mid_via_offset, b_pos])
-            contact_offset = b_pos - vector(0.5 * contact.m1m2.height, 0)
+            contact_offset = b_pos - vector(0.5 * contact.m1_via.height, 0)
             self.add_via_center(layers=self.m1_stack,
                                 offset=contact_offset,
                                 directions=("H", "H"))