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Second iteration try unblocking partial blocked grids.

This commit is contained in:
mrg 2021-01-13 12:37:29 -08:00
parent 4991693f1a
commit 78966824db
1 changed files with 25 additions and 17 deletions
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40
compiler/router/supply_tree_router.py
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@ -122,27 +122,35 @@ class supply_tree_router(router):
def route_signal(self, pin_name, src_idx, dest_idx): def route_signal(self, pin_name, src_idx, dest_idx):
for detour_scale in [5 * pow(2, x) for x in range(5)]: # First pass, try to route normally
debug.info(2, "Routing {0} to {1} with scale {2}".format(src_idx, dest_idx, detour_scale)) # Second pass, clear prior pin blockages so that you can route over other metal
# of the same supply. Otherwise, this can create a lot of circular routes due to accidental overlaps.
for unblock_routes in [False, True]:
for detour_scale in [5 * pow(2, x) for x in range(5)]:
debug.info(2, "Routing {0} to {1} with scale {2}".format(src_idx, dest_idx, detour_scale))
# Clear everything in the routing grid. # Clear everything in the routing grid.
self.rg.reinit() self.rg.reinit()
# This is inefficient since it is non-incremental, but it was # This is inefficient since it is non-incremental, but it was
# easier to debug. # easier to debug.
self.prepare_blockages() self.prepare_blockages()
self.clear_blockages(pin_name) if unblock_routes:
self.set_blockages(self.path_blockages, False)
# Add the single component of the pin as the source # Add the single component of the pin as the source
# which unmarks it as a blockage too # which unmarks it as a blockage too
self.add_pin_component_source(pin_name, src_idx) self.add_pin_component_source(pin_name, src_idx)
# Marks all pin components except index as target # Marks all pin components except index as target
self.add_pin_component_target(pin_name, dest_idx) self.add_pin_component_target(pin_name, dest_idx)
# Actually run the A* router # Actually run the A* router
if self.run_router(detour_scale=detour_scale): if self.run_router(detour_scale=detour_scale):
return return
debug.warning("Unblocking supply self blockages to improve access (may cause DRC errors):\n{0}\n{1})".format(pin_name,
self.pin_groups[pin_name][src_idx].pins))
self.write_debug_gds("debug_route.gds", True) self.write_debug_gds("debug_route.gds", True)