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OpenRAM
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4-bank SRAMs are now working.

This commit is contained in:
Matt Guthaus 2017-10-04 18:05:45 -07:00
parent 21c77645d3
commit 788f3d9122
3 changed files with 443 additions and 673 deletions
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4
compiler/bank.py
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@ -93,9 +93,6 @@ class bank(design.design):
self.route_vdd_supply() self.route_vdd_supply()
self.route_gnd_supply() self.route_gnd_supply()
def add_modules(self): def add_modules(self):
""" Add modules. The order should not matter! """ """ Add modules. The order should not matter! """
self.add_bitcell_array() self.add_bitcell_array()
@ -432,7 +429,6 @@ class bank(design.design):
temp.extend(["vdd", "gnd"]) temp.extend(["vdd", "gnd"])
self.connect_inst(temp) self.connect_inst(temp)
def add_column_decoder(self): def add_column_decoder(self):
""" Create a 2:4 decoder to decode column select lines if the col_addr_size = 4 """ """ Create a 2:4 decoder to decode column select lines if the col_addr_size = 4 """

1076
compiler/sram.py
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File diff suppressed because it is too large Load Diff

6
compiler/tests/20_sram_4bank_test.py
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@ -26,15 +26,15 @@ class sram_4bank_test(unittest.TestCase):
import sram import sram
debug.info(1, "Four bank, no column mux with control logic") debug.info(1, "Four bank, no column mux with control logic")
a = sram.sram(word_size=4, num_words=32, num_banks=4, name="sram1") a = sram.sram(word_size=16, num_words=64, num_banks=4, name="sram1")
self.local_check(a) self.local_check(a)
debug.info(1, "Four bank two way column mux with control logic") debug.info(1, "Four bank two way column mux with control logic")
a = sram.sram(word_size=4, num_words=64, num_banks=4, name="sram2") a = sram.sram(word_size=16, num_words=128, num_banks=4, name="sram2")
self.local_check(a) self.local_check(a)
debug.info(1, "Four bank, four way column mux with control logic") debug.info(1, "Four bank, four way column mux with control logic")
a = sram.sram(word_size=4, num_words=128, num_banks=4, name="sram3") a = sram.sram(word_size=16, num_words=256, num_banks=4, name="sram3")
self.local_check(a) self.local_check(a)
# debug.info(1, "Four bank, eight way column mux with control logic") # debug.info(1, "Four bank, eight way column mux with control logic")