mirror of https://github.com/VLSIDA/OpenRAM.git
hard-code multi-delay stages
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@ -151,7 +151,7 @@ class control_logic_delay(design.design):
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debug.check(OPTS.delay_chain_stages % 2,
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debug.check(OPTS.delay_chain_stages % 2,
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"Must use odd number of delay chain stages for inverting delay chain.")
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"Must use odd number of delay chain stages for inverting delay chain.")
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self.multi_delay_chain=factory.create(module_type = "multi_delay_chain",
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self.multi_delay_chain=factory.create(module_type = "multi_delay_chain",
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fanout_list = OPTS.delay_chain_stages * [ OPTS.delay_chain_fanout_per_stage ],
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fanout_list = 14 * [ OPTS.delay_chain_fanout_per_stage ],
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pinout_list = [1, 6, 7, 14]) # TODO: generate this list programatically
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pinout_list = [1, 6, 7, 14]) # TODO: generate this list programatically
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# not being used
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# not being used
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