mirror of https://github.com/VLSIDA/OpenRAM.git
Separate supply pin type from route supplies option
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013c5932a0
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@ -1190,19 +1190,19 @@ class layout():
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ll_offset = vector(0, 0)
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ll_offset = vector(0, 0)
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ur_offset = vector(0, 0)
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ur_offset = vector(0, 0)
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if side in ["ring", "top"]:
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if side in ["ring", "top", "all"]:
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ur_offset += vector(0, big_margin)
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ur_offset += vector(0, big_margin)
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else:
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else:
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ur_offset += vector(0, little_margin)
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ur_offset += vector(0, little_margin)
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if side in ["ring", "bottom"]:
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if side in ["ring", "bottom", "all"]:
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ll_offset += vector(0, big_margin)
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ll_offset += vector(0, big_margin)
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else:
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else:
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ll_offset += vector(0, little_margin)
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ll_offset += vector(0, little_margin)
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if side in ["ring", "left"]:
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if side in ["ring", "left", "all"]:
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ll_offset += vector(big_margin, 0)
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ll_offset += vector(big_margin, 0)
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else:
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else:
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ll_offset += vector(little_margin, 0)
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ll_offset += vector(little_margin, 0)
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if side in ["ring", "right"]:
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if side in ["ring", "right", "all"]:
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ur_offset += vector(big_margin, 0)
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ur_offset += vector(big_margin, 0)
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else:
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else:
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ur_offset += vector(little_margin, 0)
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ur_offset += vector(little_margin, 0)
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@ -99,6 +99,7 @@ class options(optparse.Values):
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netlist_only = False
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netlist_only = False
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# Whether we should do the final power routing
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# Whether we should do the final power routing
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route_supplies = "tree"
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route_supplies = "tree"
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supply_pin_type = "ring"
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# This determines whether LVS and DRC is checked at all.
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# This determines whether LVS and DRC is checked at all.
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check_lvsdrc = False
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check_lvsdrc = False
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# This determines whether LVS and DRC is checked for every submodule.
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# This determines whether LVS and DRC is checked for every submodule.
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@ -21,7 +21,7 @@ class supply_grid_router(router):
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routes a grid to connect the supply on the two layers.
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routes a grid to connect the supply on the two layers.
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"""
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"""
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def __init__(self, layers, design, margin=0, bbox=None):
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def __init__(self, layers, design, bbox=None, pin_type=None):
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"""
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"""
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This will route on layers in design. It will get the blockages from
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This will route on layers in design. It will get the blockages from
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either the gds file name or the design itself (by saving to a gds file).
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either the gds file name or the design itself (by saving to a gds file).
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@ -34,7 +34,7 @@ class supply_tree_router(router):
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# The pin escape router already made the bounding box big enough,
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# The pin escape router already made the bounding box big enough,
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# so we can use the regular bbox here.
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# so we can use the regular bbox here.
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if pin_type:
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if pin_type:
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debug.check(pin_type in ["left", "right", "top", "bottom", "tree", "ring"],
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debug.check(pin_type in ["left", "right", "top", "bottom", "single", "ring"],
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"Invalid pin type {}".format(pin_type))
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"Invalid pin type {}".format(pin_type))
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self.pin_type = pin_type
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self.pin_type = pin_type
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router.__init__(self,
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router.__init__(self,
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@ -75,6 +75,7 @@ class supply_tree_router(router):
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self.add_ring_supply_pin(self.vdd_name)
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self.add_ring_supply_pin(self.vdd_name)
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self.add_ring_supply_pin(self.gnd_name)
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self.add_ring_supply_pin(self.gnd_name)
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self.write_debug_gds("foo.gds", False)
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# Route the supply pins to the supply rails
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# Route the supply pins to the supply rails
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# Route vdd first since we want it to be shorter
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# Route vdd first since we want it to be shorter
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start_time = datetime.now()
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start_time = datetime.now()
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@ -9,6 +9,7 @@ from vector import vector
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from sram_base import sram_base
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from sram_base import sram_base
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from contact import m2_via
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from contact import m2_via
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from channel_route import channel_route
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from channel_route import channel_route
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from router_tech import router_tech
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from globals import OPTS
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from globals import OPTS
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@ -334,11 +335,21 @@ class sram_1bank(sram_base):
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# Route the pins to the perimeter
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# Route the pins to the perimeter
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pre_bbox = None
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pre_bbox = None
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if OPTS.perimeter_pins:
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if OPTS.perimeter_pins:
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rt = router_tech(self.supply_stack, 1)
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if OPTS.supply_pin_type in ["ring", "left", "right", "top", "bottom"]:
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big_margin = 12 * rt.track_width
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little_margin = 2 * rt.track_width
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else:
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big_margin = 6 * rt.track_width
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little_margin = 0
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pre_bbox = self.get_bbox(side="ring",
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pre_bbox = self.get_bbox(side="ring",
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big_margin=self.m3_pitch)
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big_margin=rt.track_width)
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bbox = self.get_bbox(side=OPTS.route_supplies,
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big_margin=14 * self.m3_pitch,
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bbox = self.get_bbox(side=OPTS.supply_pin_type,
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little_margin=4 * self.m3_pitch)
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big_margin=big_margin,
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little_margin=little_margin)
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self.route_escape_pins(bbox)
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self.route_escape_pins(bbox)
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# Route the supplies first since the MST is not blockage aware
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# Route the supplies first since the MST is not blockage aware
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@ -41,6 +41,14 @@ class sram_base(design, verilog, lef):
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if not self.num_spare_cols:
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if not self.num_spare_cols:
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self.num_spare_cols = 0
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self.num_spare_cols = 0
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try:
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from tech import power_grid
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self.supply_stack = power_grid
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except ImportError:
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# if no power_grid is specified by tech we use sensible defaults
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# Route a M3/M4 grid
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self.supply_stack = self.m3_stack
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def add_pins(self):
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def add_pins(self):
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""" Add pins for entire SRAM. """
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""" Add pins for entire SRAM. """
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@ -239,32 +247,21 @@ class sram_base(design, verilog, lef):
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for inst in self.insts:
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for inst in self.insts:
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self.copy_power_pins(inst, pin_name, self.ext_supply[pin_name])
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self.copy_power_pins(inst, pin_name, self.ext_supply[pin_name])
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try:
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from tech import power_grid
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grid_stack = power_grid
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except ImportError:
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# if no power_grid is specified by tech we use sensible defaults
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# Route a M3/M4 grid
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grid_stack = self.m3_stack
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if not OPTS.route_supplies:
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if not OPTS.route_supplies:
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# Do not route the power supply (leave as must-connect pins)
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# Do not route the power supply (leave as must-connect pins)
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return
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return
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elif OPTS.route_supplies == "grid":
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elif OPTS.route_supplies == "grid":
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from supply_grid_router import supply_grid_router as router
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from supply_grid_router import supply_grid_router as router
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rtr=router(layers=grid_stack,
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design=self,
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bbox=bbox)
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else:
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else:
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from supply_tree_router import supply_tree_router as router
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from supply_tree_router import supply_tree_router as router
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rtr=router(layers=grid_stack,
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rtr=router(layers=self.supply_stack,
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design=self,
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design=self,
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bbox=bbox,
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bbox=bbox,
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pin_type=OPTS.route_supplies)
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pin_type=OPTS.supply_pin_type)
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rtr.route()
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rtr.route()
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if OPTS.route_supplies in ["left", "right", "top", "bottom", "ring"]:
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if OPTS.supply_pin_type in ["left", "right", "top", "bottom", "ring"]:
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# Find the lowest leftest pin for vdd and gnd
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# Find the lowest leftest pin for vdd and gnd
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for pin_name in ["vdd", "gnd"]:
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for pin_name in ["vdd", "gnd"]:
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# Copy the pin shape(s) to rectangles
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# Copy the pin shape(s) to rectangles
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@ -286,7 +283,7 @@ class sram_base(design, verilog, lef):
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pin.width(),
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pin.width(),
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pin.height())
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pin.height())
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elif OPTS.route_supplies or OPTS.route_supplies == "single":
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elif OPTS.route_supplies and OPTS.supply_pin_type == "single":
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# Update these as we may have routed outside the region (perimeter pins)
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# Update these as we may have routed outside the region (perimeter pins)
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lowest_coord = self.find_lowest_coords()
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lowest_coord = self.find_lowest_coords()
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