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Debugging klayout for SCMOS and FreePDK45.

This commit is contained in:
mrg 2021-09-22 16:54:52 -07:00
parent 0c3ee643ab
commit 779d6ad2b2
3 changed files with 216 additions and 213 deletions
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10
technology/freepdk45/tech/freepdk45.lylvs
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@ -206,13 +206,13 @@ connect(metal10, metal10_pin)
schematic.simplify schematic.simplify
if $connect_supplies if $connect_supplies
connect_implicit("*", "vdd") connect_implicit("vdd")
connect_implicit("*", "gnd") connect_implicit("gnd")
end end
connect_global(pwell, "PWELL") #connect_global(pwell, "PWELL")
connect_global(nwell, "NWELL") #connect_global(nwell, "NWELL")
connect_global(bulk, "BULK") #connect_global(bulk, "BULK")
for pat in %w(pinv* pnor* pnand* and?_dec* write_driver* port_address* replica_bitcell_array*) for pat in %w(pinv* pnor* pnand* and?_dec* write_driver* port_address* replica_bitcell_array*)
connect_explicit(pat, [ "NWELL", "vdd" ]) connect_explicit(pat, [ "NWELL", "vdd" ])

416
technology/scn4m_subm/tech/scn4m_subm.lylvs
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@ -1,208 +1,208 @@
<?xml version="1.0" encoding="utf-8"?> <?xml version="1.0" encoding="utf-8"?>
<klayout-macro> <klayout-macro>
<description/> <description/>
<version/> <version/>
<category>lvs</category> <category>lvs</category>
<prolog/> <prolog/>
<epilog/> <epilog/>
<doc/> <doc/>
<autorun>false</autorun> <autorun>false</autorun>
<autorun-early>false</autorun-early> <autorun-early>false</autorun-early>
<shortcut/> <shortcut/>
<show-in-menu>true</show-in-menu> <show-in-menu>true</show-in-menu>
<group-name>lvs_scripts</group-name> <group-name>lvs_scripts</group-name>
<menu-path>tools_menu.lvs.end</menu-path> <menu-path>tools_menu.lvs.end</menu-path>
<interpreter>dsl</interpreter> <interpreter>dsl</interpreter>
<dsl-interpreter-name>lvs-dsl-xml</dsl-interpreter-name> <dsl-interpreter-name>lvs-dsl-xml</dsl-interpreter-name>
<text># <text>#
# Extraction for freePDK45 # Extraction for freePDK45
# #
############################ ############################
tstart = Time.now tstart = Time.now
# optionnal for a batch launch : klayout -b -rd input=my_layout.gds -rd report=my_report.lyrdb -rd schematic=reference_netlist.cir -rd target_netlist=extracted_netlist.cir -r lvs_freepdk45.lvs # optionnal for a batch launch : klayout -b -rd input=my_layout.gds -rd report=my_report.lyrdb -rd schematic=reference_netlist.cir -rd target_netlist=extracted_netlist.cir -r lvs_freepdk45.lvs
if $input if $input
source($input) source($input)
end end
if $report if $report
report_lvs($report) report_lvs($report)
else else
report_lvs("lvs_report.lvsdb") report_lvs("lvs_report.lvsdb")
end end
if $schematic if $schematic
#reference netlist #reference netlist
schematic($schematic) schematic($schematic)
else else
schematic(RBA::CellView::active.filename.sub(/\.(oas|gds|oas.gz|gds.gz)$/, ".sp")) schematic(RBA::CellView::active.filename.sub(/\.(oas|gds|oas.gz|gds.gz)$/, ".sp"))
end end
# true: use net names instead of numbers # true: use net names instead of numbers
# false: use numbers for nets # false: use numbers for nets
spice_with_net_names = true spice_with_net_names = true
# true: put in comments with details # true: put in comments with details
# false: no comments # false: no comments
spice_with_comments = true spice_with_comments = true
if $target_netlist if $target_netlist
target_netlist($target_netlist) target_netlist($target_netlist)
else else
# target_netlist("netlist.cir", write_spice(spice_with_net_names, spice_with_comments), "The netlist comment goes here.") # target_netlist("netlist.cir", write_spice(spice_with_net_names, spice_with_comments), "The netlist comment goes here.")
target_netlist(File.join(File.dirname(RBA::CellView::active.filename), source.cell_name+"_extracted.cir"), write_spice(spice_with_net_names, spice_with_comments), "Extracted by KLayout on : #{Time.now.strftime("%d/%m/%Y %H:%M")}") target_netlist(File.join(File.dirname(RBA::CellView::active.filename), source.cell_name+"_extracted.cir"), write_spice(spice_with_net_names, spice_with_comments), "Extracted by KLayout on : #{Time.now.strftime("%d/%m/%Y %H:%M")}")
end end
# Hierarchical mode # Hierarchical mode
deep deep
# Use 4 CPU cores # Use 4 CPU cores
threads(4) threads(4)
# Print details # Print details
verbose(true) verbose(true)
# layers definitions # layers definitions
######################## ########################
info("Layers definitions") info("Layers definitions")
DNW = input(38,0) DNW = input(38,0)
nwell = input(42,0) nwell = input(42,0)
pwell = input(41,0) pwell = input(41,0)
CW = input(59,0) CW = input(59,0)
active = input(43,0) active = input(43,0)
TA = input(60,0) TA = input(60,0)
PBase = input(58,0) PBase = input(58,0)
poly = input(46,0) poly = input(46,0)
SB = input(29,0) SB = input(29,0)
nplus = input(45,0) nplus = input(45,0)
pplus = input(44,0) pplus = input(44,0)
PO2 = input(56,0) PO2 = input(56,0)
HR = input(34,0) HR = input(34,0)
Contact = input(25,0) Contact = input(25,0)
ContactPoly = input(47,0) ContactPoly = input(47,0)
ContactActive = input(48,0) ContactActive = input(48,0)
ContactPoly2 = input(55, 0) ContactPoly2 = input(55, 0)
CT = Contact + ContactPoly + ContactActive + ContactPoly2 CT = Contact + ContactPoly + ContactActive + ContactPoly2
M1 = input(49,0) M1 = input(49,0)
V1 = input(50,0) V1 = input(50,0)
M2 = input(51,0) M2 = input(51,0)
V2 = input(61,0) V2 = input(61,0)
M3 = input(62,0) M3 = input(62,0)
V3 = input(30,0) V3 = input(30,0)
M4 = input(31,0) M4 = input(31,0)
CTM = input(35,0) CTM = input(35,0)
V4 = input(32,0) V4 = input(32,0)
M5 = input(33,0) M5 = input(33,0)
V5 = input(36,0) V5 = input(36,0)
M6 = input(37,0) M6 = input(37,0)
Glass = input(52,0) Glass = input(52,0)
Pads = input(26,0) Pads = input(26,0)
# layers processing # layers processing
######################## ########################
info("Layers processing") info("Layers processing")
# Bulk layer for terminal provisioning # Bulk layer for terminal provisioning
bulk = polygon_layer bulk = polygon_layer
active_in_nwell = active &amp; nwell active_in_nwell = active &amp; nwell
pactive = active_in_nwell &amp; pplus pactive = active_in_nwell &amp; pplus
ntie = active_in_nwell &amp; nplus ntie = active_in_nwell &amp; nplus
pgate = pactive &amp; poly pgate = pactive &amp; poly
psd = pactive - pgate psd = pactive - pgate
active_in_pwell = active &amp; pwell active_in_pwell = active &amp; pwell
nactive = active_in_pwell &amp; nplus nactive = active_in_pwell &amp; nplus
ptie = active_in_pwell &amp; pplus ptie = active_in_pwell &amp; pplus
ngate = nactive &amp; poly ngate = nactive &amp; poly
nsd = nactive - ngate nsd = nactive - ngate
cheat("cell_1rw", "dummy_cell_1rw", "replica_cell_1rw", "cell_2rw", "dummy_cell_2rw", "replica_cell_2rw", "pbitcell", "dummy_pbitcell", "replica_pbitcell", "dff", "wordline_driver*") { cheat("cell_1rw", "dummy_cell_1rw", "replica_cell_1rw", "cell_2rw", "dummy_cell_2rw", "replica_cell_2rw", "pbitcell", "dummy_pbitcell", "replica_pbitcell", "dff", "wordline_driver*") {
# PMOS transistor device extraction # PMOS transistor device extraction
extract_devices(mos4("p"), { "SD" =&gt; psd, "G" =&gt; pgate, "tS" =&gt; psd, "tD" =&gt; psd, "tG" =&gt; poly, "W" =&gt; nwell }) extract_devices(mos4("p"), { "SD" =&gt; psd, "G" =&gt; pgate, "tS" =&gt; psd, "tD" =&gt; psd, "tG" =&gt; poly, "W" =&gt; nwell })
# NMOS transistor device extraction # NMOS transistor device extraction
extract_devices(mos4("n"), { "SD" =&gt; nsd, "G" =&gt; ngate, "tS" =&gt; nsd, "tD" =&gt; nsd, "tG" =&gt; poly, "W" =&gt; pwell }) extract_devices(mos4("n"), { "SD" =&gt; nsd, "G" =&gt; ngate, "tS" =&gt; nsd, "tD" =&gt; nsd, "tG" =&gt; poly, "W" =&gt; pwell })
} }
# Define connectivity for netlist extraction # Define connectivity for netlist extraction
# Inter-layer # Inter-layer
connect(nwell, ntie) connect(nwell, ntie)
connect(pwell, ptie) connect(pwell, ptie)
connect(CT, ntie) connect(CT, ntie)
connect(CT, ptie) connect(CT, ptie)
connect(psd, CT) connect(psd, CT)
connect(nsd, CT) connect(nsd, CT)
connect(poly, CT) connect(poly, CT)
connect(CT, M1) connect(CT, M1)
connect(CT, M1) connect(CT, M1)
connect(M1, V1) connect(M1, V1)
connect(V1, M2) connect(V1, M2)
connect(M2, V2) connect(M2, V2)
connect(V2, M3) connect(V2, M3)
connect(M3, V3) connect(M3, V3)
connect(V3, M4) connect(V3, M4)
connect(M4, V4) connect(M4, V4)
connect(V4, M5) connect(V4, M5)
connect(M5, V5) connect(M5, V5)
connect(V5, M6) connect(V5, M6)
# Global # Global
schematic.simplify schematic.simplify
if $connect_supplies if $connect_supplies
connect_implicit("vdd") connect_implicit("vdd")
connect_implicit("gnd") connect_implicit("gnd")
end end
connect_global(pwell, "PWELL") connect_global(pwell, "PWELL")
connect_global(nwell, "NWELL") connect_global(nwell, "NWELL")
#connect_global(bulk, "BULK") #connect_global(bulk, "BULK")
for pat in %w(pinv* pnor* pnand* and?_dec* write_driver* port_address* replica_bitcell_array*) for pat in %w(pinv* pnor* pnand* and?_dec* write_driver* port_address* replica_bitcell_array*)
connect_explicit(pat, [ "NWELL", "vdd" ]) connect_explicit(pat, [ "NWELL", "vdd" ])
connect_explicit(pat, [ "BULK", "PWELL", "gnd" ]) connect_explicit(pat, [ "BULK", "PWELL", "gnd" ])
end end
# Actually performs the extraction # Actually performs the extraction
netlist # ... not really required netlist # ... not really required
# Flatten cells which are present in one netlist only # Flatten cells which are present in one netlist only
align align
# SIMPLIFICATION of the netlist # SIMPLIFICATION of the netlist
#netlist.make_top_level_pins #netlist.make_top_level_pins
#netlist.combine_devices #netlist.combine_devices
#netlist.purge #netlist.purge
#netlist.purge_nets #netlist.purge_nets
netlist.simplify netlist.simplify
# Tolerances for the devices extracted parameters # Tolerances for the devices extracted parameters
# tolerance(device_class_name, parameter_name [, :absolute =&gt; absolute_tolerance] [, :relative =&gt; relative_tolerance]) # tolerance(device_class_name, parameter_name [, :absolute =&gt; absolute_tolerance] [, :relative =&gt; relative_tolerance])
tolerance("P", "W", :absolute =&gt; 1.nm, :relative =&gt; 0.001) tolerance("P", "W", :absolute =&gt; 1.nm, :relative =&gt; 0.001)
tolerance("N", "W", :absolute =&gt; 1.nm, :relative =&gt; 0.001) tolerance("N", "W", :absolute =&gt; 1.nm, :relative =&gt; 0.001)
#max_res(1000000) #max_res(1000000)
#min_caps(1e-15) #min_caps(1e-15)
max_branch_complexity(65536) max_branch_complexity(65536)
max_depth(16) max_depth(16)
if ! compare if ! compare
#raise "ERROR : Netlists don't match" #raise "ERROR : Netlists don't match"
puts "ERROR : Netlists don't match" puts "ERROR : Netlists don't match"
else else
puts "CONGRATULATIONS! Netlists match." puts "CONGRATULATIONS! Netlists match."
end end
# time spent for the LVS # time spent for the LVS
time = Time.now time = Time.now
hours = ((time - tstart)/3600).to_i hours = ((time - tstart)/3600).to_i
minutes = ((time - tstart)/60 - hours * 60).to_i minutes = ((time - tstart)/60 - hours * 60).to_i
seconds = ((time - tstart) - (minutes * 60 + hours * 3600)).to_i seconds = ((time - tstart) - (minutes * 60 + hours * 3600)).to_i
$stdout.write "LVS finished at : #{time.hour}:#{time.min}:#{time.sec} - LVS duration = #{hours} hrs. #{minutes} min. #{seconds} sec.\n"</text> $stdout.write "LVS finished at : #{time.hour}:#{time.min}:#{time.sec} - LVS duration = #{hours} hrs. #{minutes} min. #{seconds} sec.\n"</text>
</klayout-macro> </klayout-macro>

3
technology/scn4m_subm/tech/tech.py
View File

@ -428,5 +428,8 @@ spice["sa_transconductance"] = (spice["mobility_n"])*spice["cox"]*(parameter["sa
drc_name = "magic" drc_name = "magic"
lvs_name = "netgen" lvs_name = "netgen"
pex_name = "magic" pex_name = "magic"
drc_name = "klayout"
lvs_name = "klayout"
pex_name = "klayout"
blackbox_bitcell = False blackbox_bitcell = False