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Debugging klayout for SCMOS and FreePDK45.

This commit is contained in:
mrg 2021-09-22 16:54:52 -07:00
parent 0c3ee643ab
commit 779d6ad2b2
3 changed files with 216 additions and 213 deletions
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10
technology/freepdk45/tech/freepdk45.lylvs
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@ -206,13 +206,13 @@ connect(metal10, metal10_pin)
schematic.simplify schematic.simplify
if $connect_supplies if $connect_supplies
connect_implicit("*", "vdd") connect_implicit("vdd")
connect_implicit("*", "gnd") connect_implicit("gnd")
end end
connect_global(pwell, "PWELL") #connect_global(pwell, "PWELL")
connect_global(nwell, "NWELL") #connect_global(nwell, "NWELL")
connect_global(bulk, "BULK") #connect_global(bulk, "BULK")
for pat in %w(pinv* pnor* pnand* and?_dec* write_driver* port_address* replica_bitcell_array*) for pat in %w(pinv* pnor* pnand* and?_dec* write_driver* port_address* replica_bitcell_array*)
connect_explicit(pat, [ "NWELL", "vdd" ]) connect_explicit(pat, [ "NWELL", "vdd" ])

3
technology/scn4m_subm/tech/tech.py
View File

@ -428,5 +428,8 @@ spice["sa_transconductance"] = (spice["mobility_n"])*spice["cox"]*(parameter["sa
drc_name = "magic" drc_name = "magic"
lvs_name = "netgen" lvs_name = "netgen"
pex_name = "magic" pex_name = "magic"
drc_name = "klayout"
lvs_name = "klayout"
pex_name = "klayout"
blackbox_bitcell = False blackbox_bitcell = False