mirror of https://github.com/VLSIDA/OpenRAM.git
Only do one extract. Flatten transistors since bug fixed in magic.
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parent
910bcf9df3
commit
76bc4e1fc2
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@ -96,7 +96,7 @@ def write_drc_script(cell_name, gds_name, extract, final_verification, output_pa
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f.write("gds warning default\n")
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f.write("gds warning default\n")
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# Flatten the transistors
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# Flatten the transistors
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# Bug in Netgen 1.5.194 when using this...
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# Bug in Netgen 1.5.194 when using this...
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#f.write("gds flatglob *_?mos_m*\n")
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f.write("gds flatglob *_?mos_m*\n")
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# These two options are temporarily disabled until Tim fixes a bug in magic related
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# These two options are temporarily disabled until Tim fixes a bug in magic related
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# to flattening channel routes and vias (hierarchy with no devices in it). Otherwise,
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# to flattening channel routes and vias (hierarchy with no devices in it). Otherwise,
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# they appear to be disconnected.
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# they appear to be disconnected.
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@ -119,11 +119,12 @@ def write_drc_script(cell_name, gds_name, extract, final_verification, output_pa
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pre = "#"
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pre = "#"
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else:
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else:
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pre = ""
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pre = ""
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if final_verification and OPTS.route_supplies:
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f.write(pre + "extract unique all\n")
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# Hack to work around unit scales in SkyWater
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# Hack to work around unit scales in SkyWater
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if OPTS.tech_name=="sky130":
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if OPTS.tech_name=="sky130":
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f.write(pre + "extract style ngspice(si)\n")
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f.write(pre + "extract style ngspice(si)\n")
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if final_verification and OPTS.route_supplies:
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f.write(pre + "extract unique all\n")
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else:
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f.write(pre + "extract all\n")
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f.write(pre + "extract all\n")
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f.write(pre + "select top cell\n")
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f.write(pre + "select top cell\n")
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f.write(pre + "feedback why\n")
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f.write(pre + "feedback why\n")
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