Update golden lib tests. Add new generic SCMOS models. Fix tech error with new msflop_in_cap name.

compiler/modules/control_logic.py

@@ -69,7 +69,7 @@ class control_logic(design.design):
         c = reload(__import__(OPTS.replica_bitline))
         replica_bitline = getattr(c, OPTS.replica_bitline)
         # FIXME: These should be tuned according to the size!
-        FO4_stages = 4
+        FO4_stages = 8
         bitcell_loads = int(math.ceil(self.num_rows / 10.0))
         self.replica_bitline = replica_bitline(FO4_stages, bitcell_loads)
         self.add_mod(self.replica_bitline)

compiler/modules/delay_chain.py

@@ -8,7 +8,8 @@ from globals import OPTS
 
 class delay_chain(design.design):
     """
-    Generate a logic effort based delay chain.
+    Generate a delay chain with the given number of stages and fanout.
+    This automatically adds an extra inverter with no load on the input.
     Input is a list contains the electrical effort of each stage.
     """