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fix precharge bit offsets in no rbl case

This commit is contained in:
Sam Crow 2023-04-25 09:24:18 -07:00
parent eea748ff3e
commit 744ba0e892
1 changed files with 9 additions and 6 deletions
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15
compiler/modules/port_data.py
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@ -204,12 +204,15 @@ class port_data(design):
precharge_width = cell.width + strap.width precharge_width = cell.width + strap.width
else: else:
precharge_width = cell.width precharge_width = cell.width
if self.port == 0: if self.has_rbl:
# Append an offset on the left if self.port == 0:
precharge_bit_offsets = [self.bit_offsets[0] - precharge_width] + self.bit_offsets # Append an offset on the left
precharge_bit_offsets = [self.bit_offsets[0] - precharge_width] + self.bit_offsets
else:
# Append an offset on the right
precharge_bit_offsets = self.bit_offsets + [self.bit_offsets[-1] + precharge_width]
else: else:
# Append an offset on the right precharge_bit_offsets = self.bit_offsets
precharge_bit_offsets = self.bit_offsets + [self.bit_offsets[-1] + precharge_width]
# has_rbl is a boolean treated as 1 if true 0 if false typical python # has_rbl is a boolean treated as 1 if true 0 if false typical python
self.precharge_array = factory.create(module_type="precharge_array", self.precharge_array = factory.create(module_type="precharge_array",
@ -561,7 +564,7 @@ class port_data(design):
inst1 = self.precharge_array_inst inst1 = self.precharge_array_inst
inst1_bls_templ="{inst}_{bit}" inst1_bls_templ="{inst}_{bit}"
if self.port==0: if self.port==0 and self.has_rbl:
start_bit=1 start_bit=1
else: else:
start_bit=0 start_bit=0