mirror of https://github.com/VLSIDA/OpenRAM.git
Small change to test webhook
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@ -7,7 +7,6 @@ a spice (.sp) file for circuit simulation
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a GDS2 (.gds) file containing the layout
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a GDS2 (.gds) file containing the layout
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a LEF (.lef) file for preliminary P&R (real one should be from layout)
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a LEF (.lef) file for preliminary P&R (real one should be from layout)
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a Liberty (.lib) file for timing analysis/optimization
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a Liberty (.lib) file for timing analysis/optimization
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"""
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"""
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import sys,os
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import sys,os
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