mirror of https://github.com/VLSIDA/OpenRAM.git
Removed dead code related to older characterization scheme
This commit is contained in:
Hunter Nichols
parent
42f2ff679e
commit
73b2277daa
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@ -55,12 +55,6 @@ class dff(design.design):
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transition_prob = 0.5
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return transition_prob*(c_load + c_para)
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def get_clk_cin(self):
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"""Return the total capacitance (in relative units) that the clock is loaded by in the dff"""
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#This is a handmade cell so the value must be entered in the tech.py file or estimated.
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#Calculated in the tech file by summing the widths of all the gates and dividing by the minimum width.
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return parameter["dff_clk_cin"]
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def build_graph(self, graph, inst_name, port_nets):
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"""Adds edges based on inputs/outputs. Overrides base class function."""
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self.add_graph_edges(graph, port_nets)
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@ -1039,42 +1039,6 @@ class bank(design.design):
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self.add_via_center(layers=self.m1_stack,
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offset=control_pos)
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def determine_wordline_stage_efforts(self, external_cout, inp_is_rise=True):
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"""Get the all the stage efforts for each stage in the path within the bank clk_buf to a wordline"""
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# Decoder is assumed to have settled before the negative edge of the clock.
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# Delay model relies on this assumption
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stage_effort_list = []
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wordline_cout = self.bitcell_array.get_wordline_cin() + external_cout
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stage_effort_list += self.port_address.wordline_driver.determine_wordline_stage_efforts(wordline_cout,
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inp_is_rise)
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return stage_effort_list
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def get_wl_en_cin(self):
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"""Get the relative capacitance of all the clk connections in the bank"""
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# wl_en only used in the wordline driver.
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return self.port_address.wordline_driver.get_wl_en_cin()
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def get_w_en_cin(self):
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"""Get the relative capacitance of all the clk connections in the bank"""
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# wl_en only used in the wordline driver.
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port = self.write_ports[0]
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return self.port_data[port].write_driver.get_w_en_cin()
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def get_clk_bar_cin(self):
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"""Get the relative capacitance of all the clk_bar connections in the bank"""
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# Current bank only uses clock bar (clk_buf_bar) as an enable for the precharge array.
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# Precharges are the all the same in Mulitport, one is picked
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port = self.read_ports[0]
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return self.port_data[port].precharge_array.get_en_cin()
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def get_sen_cin(self):
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"""Get the relative capacitance of all the sense amp enable connections in the bank"""
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# Current bank only uses sen as an enable for the sense amps.
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port = self.read_ports[0]
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return self.port_data[port].sense_amp_array.get_en_cin()
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def graph_exclude_precharge(self):
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"""Precharge adds a loop between bitlines, can be excluded to reduce complexity"""
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for port in self.read_ports:
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@ -97,13 +97,6 @@ class bitcell_array(bitcell_base_array):
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bl_wire.wire_c =spice["min_tx_drain_c"] + bl_wire.wire_c
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return bl_wire
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def get_wordline_cin(self):
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"""Get the relative input capacitance from the wordline connections in all the bitcell"""
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# A single wordline is connected to all the bitcells in a single row meaning the capacitance depends on the # of columns
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bitcell_wl_cin = self.cell.get_wl_cin()
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total_cin = bitcell_wl_cin * self.column_size
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return total_cin
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def graph_exclude_bits(self, targ_row, targ_col):
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"""Excludes bits in column from being added to graph except target"""
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# Function is not robust with column mux configurations
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@ -157,96 +157,12 @@ class control_logic(design.design):
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height=dff_height)
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self.add_mod(self.nand2)
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# if (self.port_type == "rw") or (self.port_type == "r"):
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# from importlib import reload
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# self.delay_chain_resized = False
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# c = reload(__import__(OPTS.replica_bitline))
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# replica_bitline = getattr(c, OPTS.replica_bitline)
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# bitcell_loads = int(math.ceil(self.num_rows * OPTS.rbl_delay_percentage))
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# #Use a model to determine the delays with that heuristic
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# if OPTS.use_tech_delay_chain_size: #Use tech parameters if set.
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# fanout_list = OPTS.delay_chain_stages*[OPTS.delay_chain_fanout_per_stage]
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# debug.info(1, "Using tech parameters to size delay chain: fanout_list={}".format(fanout_list))
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# self.replica_bitline = factory.create(module_type="replica_bitline",
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# delay_fanout_list=fanout_list,
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# bitcell_loads=bitcell_loads)
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# if self.sram != None: #Calculate model value even for specified sizes
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# self.set_sen_wl_delays()
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# else: #Otherwise, use a heuristic and/or model based sizing.
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# #First use a heuristic
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# delay_stages_heuristic, delay_fanout_heuristic = self.get_heuristic_delay_chain_size()
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# self.replica_bitline = factory.create(module_type="replica_bitline",
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# delay_fanout_list=[delay_fanout_heuristic]*delay_stages_heuristic,
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# bitcell_loads=bitcell_loads)
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# #Resize if necessary, condition depends on resizing method
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# if self.sram != None and self.enable_delay_chain_resizing and not self.does_sen_rise_fall_timing_match():
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# #This resizes to match fall and rise delays, can make the delay chain weird sizes.
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# stage_list = self.get_dynamic_delay_fanout_list(delay_stages_heuristic, delay_fanout_heuristic)
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# self.replica_bitline = factory.create(module_type="replica_bitline",
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# delay_fanout_list=stage_list,
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# bitcell_loads=bitcell_loads)
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# #This resizes based on total delay.
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# # delay_stages, delay_fanout = self.get_dynamic_delay_chain_size(delay_stages_heuristic, delay_fanout_heuristic)
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# # self.replica_bitline = factory.create(module_type="replica_bitline",
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# # delay_fanout_list=[delay_fanout]*delay_stages,
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# # bitcell_loads=bitcell_loads)
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# self.sen_delay_rise,self.sen_delay_fall = self.get_delays_to_sen() #get the new timing
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# self.delay_chain_resized = True
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debug.check(OPTS.delay_chain_stages % 2,
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"Must use odd number of delay chain stages for inverting delay chain.")
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self.delay_chain=factory.create(module_type="delay_chain",
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fanout_list = OPTS.delay_chain_stages * [ OPTS.delay_chain_fanout_per_stage ])
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self.add_mod(self.delay_chain)
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def get_heuristic_delay_chain_size(self):
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"""Use a basic heuristic to determine the size of the delay chain used for the Sense Amp Enable """
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# FIXME: The minimum was 2 fanout, now it will not pass DRC unless it is 3. Why?
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delay_fanout = 3 # This can be anything >=3
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# Model poorly captures delay of the column mux. Be pessismistic for column mux
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if self.words_per_row >= 2:
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delay_stages = 8
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else:
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delay_stages = 2
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# Read ports have a shorter s_en delay. The model is not accurate enough to catch this difference
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# on certain sram configs.
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if self.port_type == "r":
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delay_stages+=2
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return (delay_stages, delay_fanout)
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def set_sen_wl_delays(self):
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"""Set delays for wordline and sense amp enable"""
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self.wl_delay_rise, self.wl_delay_fall = self.get_delays_to_wl()
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self.sen_delay_rise, self.sen_delay_fall = self.get_delays_to_sen()
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self.wl_delay = self.wl_delay_rise + self.wl_delay_fall
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self.sen_delay = self.sen_delay_rise + self.sen_delay_fall
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def does_sen_rise_fall_timing_match(self):
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"""Compare the relative rise/fall delays of the sense amp enable and wordline"""
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self.set_sen_wl_delays()
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# This is not necessarily more reliable than total delay in some cases.
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if (self.wl_delay_rise * self.wl_timing_tolerance >= self.sen_delay_rise or
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self.wl_delay_fall * self.wl_timing_tolerance >= self.sen_delay_fall):
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return False
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else:
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return True
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def does_sen_total_timing_match(self):
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"""Compare the total delays of the sense amp enable and wordline"""
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self.set_sen_wl_delays()
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# The sen delay must always be bigger than than the wl
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# delay. This decides how much larger the sen delay must be
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# before a re-size is warranted.
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if self.wl_delay * self.wl_timing_tolerance >= self.sen_delay:
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return False
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else:
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return True
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def get_dynamic_delay_chain_size(self, previous_stages, previous_fanout):
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"""Determine the size of the delay chain used for the Sense Amp Enable using path delays"""
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from math import ceil
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@ -334,17 +250,6 @@ class control_logic(design.design):
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delay_stages = ceil(required_delay / delay_per_stage)
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return delay_stages
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def calculate_stage_list(self, total_stages, fanout_rise, fanout_fall):
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"""
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Produces a list of fanouts which determine the size of the delay chain.
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List length is the number of stages.
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Assumes the first stage is falling.
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"""
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stage_list = []
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for i in range(total_stages):
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if i % 2 == 0:
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stage_list.append()
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def setup_signal_busses(self):
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""" Setup bus names, determine the size of the busses etc """
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@ -869,137 +774,6 @@ class control_logic(design.design):
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offset=pin.ll(),
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height=pin.height(),
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width=pin.width())
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def get_delays_to_wl(self):
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"""Get the delay (in delay units) of the clk to a wordline in the bitcell array"""
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debug.check(self.sram.all_mods_except_control_done, "Cannot calculate sense amp enable delay unless all module have been added.")
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self.wl_stage_efforts = self.get_wordline_stage_efforts()
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clk_to_wl_rise, clk_to_wl_fall = logical_effort.calculate_relative_rise_fall_delays(self.wl_stage_efforts)
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total_delay = clk_to_wl_rise + clk_to_wl_fall
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debug.info(1,
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"Clock to wl delay is rise={:.3f}, fall={:.3f}, total={:.3f} in delay units".format(clk_to_wl_rise,
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clk_to_wl_fall,
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total_delay))
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return clk_to_wl_rise, clk_to_wl_fall
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def get_wordline_stage_efforts(self):
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"""Follows the gated_clk_bar -> wl_en -> wordline signal for the total path efforts"""
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stage_effort_list = []
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# Initial direction of gated_clk_bar signal for this path
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is_clk_bar_rise = True
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# Calculate the load on wl_en within the module and add it to external load
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external_cout = self.sram.get_wl_en_cin()
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# First stage is the clock buffer
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stage_effort_list += self.clk_buf_driver.get_stage_efforts(external_cout, is_clk_bar_rise)
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last_stage_is_rise = stage_effort_list[-1].is_rise
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# Then ask the sram for the other path delays (from the bank)
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stage_effort_list += self.sram.get_wordline_stage_efforts(last_stage_is_rise)
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return stage_effort_list
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def get_delays_to_sen(self):
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"""
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Get the delay (in delay units) of the clk to a sense amp enable.
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This does not incorporate the delay of the replica bitline.
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"""
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debug.check(self.sram.all_mods_except_control_done, "Cannot calculate sense amp enable delay unless all module have been added.")
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self.sen_stage_efforts = self.get_sa_enable_stage_efforts()
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clk_to_sen_rise, clk_to_sen_fall = logical_effort.calculate_relative_rise_fall_delays(self.sen_stage_efforts)
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total_delay = clk_to_sen_rise + clk_to_sen_fall
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debug.info(1,
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"Clock to s_en delay is rise={:.3f}, fall={:.3f}, total={:.3f} in delay units".format(clk_to_sen_rise,
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clk_to_sen_fall,
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total_delay))
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return clk_to_sen_rise, clk_to_sen_fall
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def get_sa_enable_stage_efforts(self):
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"""Follows the gated_clk_bar signal to the sense amp enable signal adding each stages stage effort to a list"""
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stage_effort_list = []
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# Initial direction of clock signal for this path
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last_stage_rise = True
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# First stage, gated_clk_bar -(and2)-> rbl_in. Only for RW ports.
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if self.port_type == "rw":
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stage1_cout = self.replica_bitline.get_en_cin()
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stage_effort_list += self.and2.get_stage_efforts(stage1_cout, last_stage_rise)
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last_stage_rise = stage_effort_list[-1].is_rise
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# Replica bitline stage, rbl_in -(rbl)-> pre_s_en
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stage2_cout = self.sen_and2.get_cin()
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stage_effort_list += self.replica_bitline.determine_sen_stage_efforts(stage2_cout, last_stage_rise)
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last_stage_rise = stage_effort_list[-1].is_rise
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# buffer stage, pre_s_en -(buffer)-> s_en
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stage3_cout = self.sram.get_sen_cin()
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stage_effort_list += self.s_en_driver.get_stage_efforts(stage3_cout, last_stage_rise)
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last_stage_rise = stage_effort_list[-1].is_rise
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return stage_effort_list
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def get_wl_sen_delays(self):
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""" Gets a list of the stages and delays in order of their path. """
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if self.sen_stage_efforts == None or self.wl_stage_efforts == None:
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debug.error("Model delays not calculated for SRAM.", 1)
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wl_delays = logical_effort.calculate_delays(self.wl_stage_efforts)
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sen_delays = logical_effort.calculate_delays(self.sen_stage_efforts)
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return wl_delays, sen_delays
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def analytical_delay(self, corner, slew, load):
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""" Gets the analytical delay from clk input to wl_en output """
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stage_effort_list = []
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# Calculate the load on clk_buf_bar
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# ext_clk_buf_cout = self.sram.get_clk_bar_cin()
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# Operations logic starts on negative edge
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last_stage_rise = False
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# First stage(s), clk -(pdriver)-> clk_buf.
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# clk_buf_cout = self.replica_bitline.get_en_cin()
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clk_buf_cout = 0
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stage_effort_list += self.clk_buf_driver.get_stage_efforts(clk_buf_cout, last_stage_rise)
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last_stage_rise = stage_effort_list[-1].is_rise
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# Second stage, clk_buf -(inv)-> clk_bar
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clk_bar_cout = self.and2.get_cin()
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stage_effort_list += self.and2.get_stage_efforts(clk_bar_cout, last_stage_rise)
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last_stage_rise = stage_effort_list[-1].is_rise
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# Third stage clk_bar -(and)-> gated_clk_bar
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gated_clk_bar_cin = self.get_gated_clk_bar_cin()
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stage_effort_list.append(self.inv.get_stage_effort(gated_clk_bar_cin, last_stage_rise))
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last_stage_rise = stage_effort_list[-1].is_rise
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# Stages from gated_clk_bar -------> wordline
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stage_effort_list += self.get_wordline_stage_efforts()
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return stage_effort_list
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def get_clk_buf_cin(self):
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"""
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Get the loads that are connected to the buffered clock.
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Includes all the DFFs and some logic.
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"""
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# Control logic internal load
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int_clk_buf_cap = self.inv.get_cin() + self.ctrl_dff_array.get_clk_cin() + self.and2.get_cin()
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# Control logic external load (in the other parts of the SRAM)
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ext_clk_buf_cap = self.sram.get_clk_bar_cin()
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return int_clk_buf_cap + ext_clk_buf_cap
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def get_gated_clk_bar_cin(self):
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"""Get intermediates net gated_clk_bar's capacitance"""
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total_cin = 0
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total_cin += self.wl_en_driver.get_cin()
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if self.port_type == 'rw':
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total_cin += self.and2.get_cin()
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return total_cin
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def graph_exclude_dffs(self):
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"""Exclude dffs from graph as they do not represent critical path"""
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@ -210,25 +210,3 @@ class delay_chain(design.design):
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layer="m2",
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start=mid_point,
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end=mid_point.scale(1, 0))
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def get_cin(self):
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"""Get the enable input ralative capacitance"""
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# Only 1 input to the delay chain which is connected to an inverter.
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dc_cin = self.inv.get_cin()
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return dc_cin
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def determine_delayed_en_stage_efforts(self, ext_delayed_en_cout, inp_is_rise=True):
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"""Get the stage efforts from the en to s_en. Does not compute the delay for the bitline load."""
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stage_effort_list = []
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# Add a stage to the list for every stage in delay chain.
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# Stages only differ in fanout except the last which has an external cout.
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last_stage_is_rise = inp_is_rise
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for stage_fanout in self.fanout_list:
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stage_cout = self.inv.get_cin() * (stage_fanout + 1)
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if len(stage_effort_list) == len(self.fanout_list) - 1:
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stage_cout+=ext_delayed_en_cout
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stage = self.inv.get_stage_effort(stage_cout, last_stage_is_rise)
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stage_effort_list.append(stage)
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last_stage_is_rise = stage.is_rise
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return stage_effort_list
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@ -155,9 +155,3 @@ class dff_array(design.design):
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self.add_via_stack_center(from_layer=clk_pin.layer,
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to_layer="m3",
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offset=vector(clk_pin.cx(), clk_ypos))
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def get_clk_cin(self):
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"""Return the total capacitance (in relative units) that the clock is loaded by in the dff array"""
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dff_clk_cin = self.dff.get_clk_cin()
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total_cin = dff_clk_cin * self.rows * self.columns
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return total_cin
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@ -196,10 +196,3 @@ class dff_buf(design.design):
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self.add_via_stack_center(from_layer=a2_pin.layer,
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to_layer="m2",
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offset=qb_pos)
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def get_clk_cin(self):
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"""Return the total capacitance (in relative units) that the clock is loaded by in the dff"""
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# This is a handmade cell so the value must be entered in the tech.py file or estimated.
|
||||
# Calculated in the tech file by summing the widths of all the gates and dividing by the minimum width.
|
||||
# FIXME: Dff changed in a past commit. The parameter need to be updated.
|
||||
return parameter["dff_clk_cin"]
|
||||
|
|
|
|||
|
|
@ -227,9 +227,3 @@ class dff_buf_array(design.design):
|
|||
# Drop a via to the M3 pin
|
||||
self.add_via_center(layers=self.m2_stack,
|
||||
offset=vector(clk_pin.cx(), clk_ypos))
|
||||
|
||||
def get_clk_cin(self):
|
||||
"""Return the total capacitance (in relative units) that the clock is loaded by in the dff array"""
|
||||
dff_clk_cin = self.dff.get_clk_cin()
|
||||
total_cin = dff_clk_cin * self.rows * self.columns
|
||||
return total_cin
|
||||
|
|
|
|||
|
|
@ -150,7 +150,3 @@ class dff_inv(design.design):
|
|||
offset=dout_pin.center())
|
||||
self.add_via_center(layers=self.m1_stack,
|
||||
offset=dout_pin.center())
|
||||
|
||||
def get_clk_cin(self):
|
||||
"""Return the total capacitance (in relative units) that the clock is loaded by in the dff"""
|
||||
return self.dff.get_clk_cin()
|
||||
|
|
|
|||
|
|
@ -189,9 +189,3 @@ class dff_inv_array(design.design):
|
|||
# Drop a via to the M3 pin
|
||||
self.add_via_center(layers=self.m2_stack,
|
||||
offset=vector(clk_pin.cx(),clk_ypos))
|
||||
|
||||
def get_clk_cin(self):
|
||||
"""Return the total capacitance (in relative units) that the clock is loaded by in the dff array"""
|
||||
dff_clk_cin = self.dff.get_clk_cin()
|
||||
total_cin = dff_clk_cin * self.rows * self.columns
|
||||
return total_cin
|
||||
|
|
|
|||
|
|
@ -54,12 +54,7 @@ class dummy_array(bitcell_base_array):
|
|||
self.connect_inst(self.get_bitcell_pins(row, col))
|
||||
|
||||
def input_load(self):
|
||||
# FIXME: This appears to be old code from previous characterization. Needs to be updated.
|
||||
wl_wire = self.gen_wl_wire()
|
||||
return wl_wire.return_input_cap()
|
||||
|
||||
def get_wordline_cin(self):
|
||||
"""Get the relative input capacitance from the wordline connections in all the bitcell"""
|
||||
# A single wordline is connected to all the bitcells in a single row meaning the capacitance depends on the # of columns
|
||||
bitcell_wl_cin = self.cell.get_wl_cin()
|
||||
total_cin = bitcell_wl_cin * self.column_size
|
||||
return total_cin
|
||||
|
|
|
|||
|
|
@ -606,11 +606,3 @@ class hierarchical_decoder(design.design):
|
|||
to_layer=self.output_layer,
|
||||
offset=rail_pos,
|
||||
directions=self.bus_directions)
|
||||
|
||||
def input_load(self):
|
||||
if self.determine_predecodes(self.num_inputs)[1]==0:
|
||||
pre = self.pre2_4
|
||||
else:
|
||||
pre = self.pre3_8
|
||||
return pre.input_load()
|
||||
|
||||
|
|
|
|||
|
|
@ -125,13 +125,3 @@ class precharge_array(design.design):
|
|||
offset = vector(tempx, 0)
|
||||
self.local_insts[i].place(offset=offset, mirror=mirror)
|
||||
xoffset = xoffset + self.pc_cell.width
|
||||
|
||||
def get_en_cin(self):
|
||||
"""
|
||||
Get the relative capacitance of all the clk connections
|
||||
in the precharge array
|
||||
"""
|
||||
# Assume single port
|
||||
precharge_en_cin = self.pc_cell.get_en_cin()
|
||||
return precharge_en_cin * self.columns
|
||||
|
||||
|
|
|
|||
|
|
@ -552,13 +552,6 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
|
|||
bl_wire.wire_c =spice["min_tx_drain_c"] + bl_wire.wire_c # 1 access tx d/s per cell
|
||||
return bl_wire
|
||||
|
||||
def get_wordline_cin(self):
|
||||
"""Get the relative input capacitance from the wordline connections in all the bitcell"""
|
||||
# A single wordline is connected to all the bitcells in a single row meaning the capacitance depends on the # of columns
|
||||
bitcell_wl_cin = self.cell.get_wl_cin()
|
||||
total_cin = bitcell_wl_cin * self.column_size
|
||||
return total_cin
|
||||
|
||||
def graph_exclude_bits(self, targ_row, targ_col):
|
||||
"""Excludes bits in column from being added to graph except target"""
|
||||
self.bitcell_array.graph_exclude_bits(targ_row, targ_col)
|
||||
|
|
|
|||
|
|
@ -83,13 +83,6 @@ class sense_amp(design.design):
|
|||
total_power = self.return_power()
|
||||
return total_power
|
||||
|
||||
def get_en_cin(self):
|
||||
"""Get the relative capacitance of sense amp enable gate cin"""
|
||||
pmos_cin = parameter["sa_en_pmos_size"] / drc("minwidth_tx")
|
||||
nmos_cin = parameter["sa_en_nmos_size"] / drc("minwidth_tx")
|
||||
# sen is connected to 2 pmos isolation TX and 1 nmos per sense amp.
|
||||
return 2 * pmos_cin + nmos_cin
|
||||
|
||||
def get_enable_name(self):
|
||||
"""Returns name used for enable net"""
|
||||
# FIXME: A better programmatic solution to designate pins
|
||||
|
|
|
|||
|
|
@ -190,18 +190,3 @@ class sense_amp_array(design.design):
|
|||
self.add_via_stack_center(from_layer=en_pin.layer,
|
||||
to_layer=self.en_layer,
|
||||
offset=inst.get_pin(self.amp.en_name).center())
|
||||
|
||||
def input_load(self):
|
||||
return self.amp.input_load()
|
||||
|
||||
def get_en_cin(self):
|
||||
"""Get the relative capacitance of all the sense amp enable connections in the array"""
|
||||
sense_amp_en_cin = self.amp.get_en_cin()
|
||||
return sense_amp_en_cin * self.word_size
|
||||
|
||||
def get_drain_cin(self):
|
||||
"""Get the relative capacitance of the drain of the PMOS isolation TX"""
|
||||
from tech import parameter
|
||||
# Bitcell drain load being used to estimate PMOS drain load
|
||||
drain_load = logical_effort.convert_farad_to_relative_c(parameter['bitcell_drain_cap'])
|
||||
return drain_load
|
||||
|
|
|
|||
|
|
@ -230,10 +230,3 @@ class single_level_column_mux_array(design.design):
|
|||
to_layer=self.sel_layer,
|
||||
offset=br_out_offset_begin,
|
||||
directions=self.via_directions)
|
||||
|
||||
def get_drain_cin(self):
|
||||
"""Get the relative capacitance of the drain of the NMOS pass TX"""
|
||||
from tech import parameter
|
||||
# Bitcell drain load being used to estimate mux NMOS drain load
|
||||
drain_load = logical_effort.convert_farad_to_relative_c(parameter['bitcell_drain_cap'])
|
||||
return drain_load
|
||||
|
|
|
|||
|
|
@ -159,24 +159,3 @@ class wordline_driver_array(design.design):
|
|||
layer=self.route_layer,
|
||||
start=wl_offset,
|
||||
end=wl_offset - vector(self.m1_width, 0))
|
||||
|
||||
def determine_wordline_stage_efforts(self, external_cout, inp_is_rise=True):
|
||||
"""
|
||||
Follows the clk_buf to a wordline signal adding
|
||||
each stages stage effort to a list.
|
||||
"""
|
||||
stage_effort_list = []
|
||||
|
||||
stage1 = self.wl_driver.get_stage_effort(external_cout, inp_is_rise)
|
||||
stage_effort_list.append(stage1)
|
||||
|
||||
return stage_effort_list
|
||||
|
||||
def get_wl_en_cin(self):
|
||||
"""
|
||||
Get the relative capacitance of all
|
||||
the enable connections in the bank
|
||||
"""
|
||||
# The enable is connected to a and2 for every row.
|
||||
total_cin = self.wl_driver.get_cin() * self.rows
|
||||
return total_cin
|
||||
|
|
|
|||
|
|
@ -265,7 +265,3 @@ class write_driver_array(design.design):
|
|||
offset=inst.get_pin(inst.mod.en_name).ll().scale(0, 1),
|
||||
width=self.width)
|
||||
|
||||
def get_w_en_cin(self):
|
||||
"""Get the relative capacitance of all the enable connections in the bank"""
|
||||
# The enable is connected to a nand2 for every row.
|
||||
return self.driver.get_w_en_cin() * len(self.driver_insts)
|
||||
|
|
|
|||
|
|
@ -140,8 +140,3 @@ class write_mask_and_array(design.design):
|
|||
supply_pin_left = self.and2_insts[0].get_pin(supply)
|
||||
supply_pin_right = self.and2_insts[self.num_wmasks - 1].get_pin(supply)
|
||||
self.add_path(supply_pin_left.layer, [supply_pin_left.lc(), supply_pin_right.rc()])
|
||||
|
||||
def get_cin(self):
|
||||
"""Get the relative capacitance of all the input connections in the bank"""
|
||||
# The enable is connected to an and2 for every row.
|
||||
return self.and2.get_cin() * len(self.and2_insts)
|
||||
|
|
|
|||
|
|
@ -147,20 +147,3 @@ class pand2(pgate.pgate):
|
|||
width=pin.width(),
|
||||
height=pin.height())
|
||||
|
||||
def get_stage_efforts(self, external_cout, inp_is_rise=False):
|
||||
"""Get the stage efforts of the A or B -> Z path"""
|
||||
stage_effort_list = []
|
||||
stage1_cout = self.inv.get_cin()
|
||||
stage1 = self.nand.get_stage_effort(stage1_cout, inp_is_rise)
|
||||
stage_effort_list.append(stage1)
|
||||
last_stage_is_rise = stage1.is_rise
|
||||
|
||||
stage2 = self.inv.get_stage_effort(external_cout, last_stage_is_rise)
|
||||
stage_effort_list.append(stage2)
|
||||
|
||||
return stage_effort_list
|
||||
|
||||
def get_cin(self):
|
||||
"""Return the relative input capacitance of a single input"""
|
||||
return self.nand.get_cin()
|
||||
|
||||
|
|
|
|||
|
|
@ -162,20 +162,3 @@ class pand3(pgate.pgate):
|
|||
load=load)
|
||||
return nand_delay + inv_delay
|
||||
|
||||
def get_stage_efforts(self, external_cout, inp_is_rise=False):
|
||||
"""Get the stage efforts of the A or B -> Z path"""
|
||||
stage_effort_list = []
|
||||
stage1_cout = self.inv.get_cin()
|
||||
stage1 = self.nand.get_stage_effort(stage1_cout, inp_is_rise)
|
||||
stage_effort_list.append(stage1)
|
||||
last_stage_is_rise = stage1.is_rise
|
||||
|
||||
stage2 = self.inv.get_stage_effort(external_cout, last_stage_is_rise)
|
||||
stage_effort_list.append(stage2)
|
||||
|
||||
return stage_effort_list
|
||||
|
||||
def get_cin(self):
|
||||
"""Return the relative input capacitance of a single input"""
|
||||
return self.nand.get_cin()
|
||||
|
||||
|
|
|
|||
|
|
@ -97,20 +97,3 @@ class pbuf(pgate.pgate):
|
|||
width=a_pin.width(),
|
||||
height=a_pin.height())
|
||||
|
||||
def get_stage_efforts(self, external_cout, inp_is_rise=False):
|
||||
"""Get the stage efforts of the A -> Z path"""
|
||||
stage_effort_list = []
|
||||
stage1_cout = self.inv2.get_cin()
|
||||
stage1 = self.inv1.get_stage_effort(stage1_cout, inp_is_rise)
|
||||
stage_effort_list.append(stage1)
|
||||
last_stage_is_rise = stage1.is_rise
|
||||
|
||||
stage2 = self.inv2.get_stage_effort(external_cout, last_stage_is_rise)
|
||||
stage_effort_list.append(stage2)
|
||||
|
||||
return stage_effort_list
|
||||
|
||||
def get_cin(self):
|
||||
"""Returns the relative capacitance of the input"""
|
||||
input_cin = self.inv1.get_cin()
|
||||
return input_cin
|
||||
|
|
|
|||
|
|
@ -169,23 +169,3 @@ class pdriver(pgate.pgate):
|
|||
""" Return the relative sizes of the buffers """
|
||||
return self.size_list
|
||||
|
||||
def get_stage_efforts(self, external_cout, inp_is_rise=False):
|
||||
""" Get the stage efforts of the A -> Z path """
|
||||
cout_list = []
|
||||
for prev_inv, inv in zip(self.inv_list, self.inv_list[1:]):
|
||||
cout_list.append(inv.get_cin())
|
||||
|
||||
cout_list.append(external_cout)
|
||||
|
||||
stage_effort_list = []
|
||||
last_inp_is_rise = inp_is_rise
|
||||
for inv, cout in zip(self.inv_list, cout_list):
|
||||
stage = inv.get_stage_effort(cout, last_inp_is_rise)
|
||||
stage_effort_list.append(stage)
|
||||
last_inp_is_rise = stage.is_rise
|
||||
|
||||
return stage_effort_list
|
||||
|
||||
def get_cin(self):
|
||||
""" Returns the relative capacitance of the input """
|
||||
return self.inv_list[0].get_cin()
|
||||
|
|
|
|||
|
|
@ -184,36 +184,3 @@ class pinvbuf(pgate.pgate):
|
|||
self.add_layout_pin_rect_center(text="A",
|
||||
layer=a_pin.layer,
|
||||
offset=a_pin.center())
|
||||
|
||||
def determine_clk_buf_stage_efforts(self, external_cout, inp_is_rise=False):
|
||||
"""Get the stage efforts of the clk -> clk_buf path"""
|
||||
stage_effort_list = []
|
||||
stage1_cout = self.inv1.get_cin() + self.inv2.get_cin()
|
||||
stage1 = self.inv.get_stage_effort(stage1_cout, inp_is_rise)
|
||||
stage_effort_list.append(stage1)
|
||||
last_stage_is_rise = stage1.is_rise
|
||||
|
||||
stage2 = self.inv2.get_stage_effort(external_cout, last_stage_is_rise)
|
||||
stage_effort_list.append(stage2)
|
||||
|
||||
return stage_effort_list
|
||||
|
||||
def determine_clk_buf_bar_stage_efforts(self, external_cout, inp_is_rise=False):
|
||||
"""Get the stage efforts of the clk -> clk_buf path"""
|
||||
|
||||
# After (almost) every stage, the direction of the signal inverts.
|
||||
stage_effort_list = []
|
||||
stage1_cout = self.inv1.get_cin() + self.inv2.get_cin()
|
||||
stage1 = self.inv.get_stage_effort(stage1_cout, inp_is_rise)
|
||||
stage_effort_list.append(stage1)
|
||||
last_stage_is_rise = stage_effort_list[-1].is_rise
|
||||
|
||||
stage2_cout = self.inv2.get_cin()
|
||||
stage2 = self.inv1.get_stage_effort(stage2_cout, last_stage_is_rise)
|
||||
stage_effort_list.append(stage2)
|
||||
last_stage_is_rise = stage_effort_list[-1].is_rise
|
||||
|
||||
stage3 = self.inv2.get_stage_effort(external_cout, last_stage_is_rise)
|
||||
stage_effort_list.append(stage3)
|
||||
|
||||
return stage_effort_list
|
||||
|
|
|
|||
|
|
@ -301,10 +301,3 @@ class precharge(design.design):
|
|||
[left_pos, right_pos],
|
||||
width=pmos_pin.height())
|
||||
|
||||
def get_en_cin(self):
|
||||
"""Get the relative capacitance of the enable in the precharge cell"""
|
||||
# The enable connect to three pmos gates
|
||||
# They all use the same size pmos.
|
||||
pmos_cin = self.pmos.get_cin()
|
||||
return 3 * pmos_cin
|
||||
|
||||
|
|
|
|||
|
|
@ -241,18 +241,3 @@ class single_level_column_mux(pgate.pgate):
|
|||
offset=vector(0, 0),
|
||||
width=self.bitcell.width,
|
||||
height=self.height)
|
||||
|
||||
def get_stage_effort(self, corner, slew, load):
|
||||
"""
|
||||
Returns relative delay that the column mux.
|
||||
Difficult to convert to LE model.
|
||||
"""
|
||||
parasitic_delay = 1
|
||||
# This is not CMOS, so using this may be incorrect.
|
||||
cin = 2 * self.tx_size
|
||||
return logical_effort.logical_effort("column_mux",
|
||||
self.tx_size,
|
||||
cin,
|
||||
load,
|
||||
parasitic_delay,
|
||||
False)
|
||||
|
|
|
|||
|
|
@ -627,20 +627,6 @@ class sram_1bank(sram_base):
|
|||
for inst in self.control_logic_insts:
|
||||
inst.mod.graph_exclude_dffs()
|
||||
|
||||
def get_sen_name(self, sram_name, port=0):
|
||||
"""Returns the s_en spice name."""
|
||||
# Naming scheme is hardcoded using this function, should be built into the
|
||||
# graph in someway.
|
||||
sen_name = "s_en{}".format(port)
|
||||
control_conns = self.get_conns(self.control_logic_insts[port])
|
||||
# Sanity checks
|
||||
if sen_name not in control_conns:
|
||||
debug.error("Signal={} not contained in control logic connections={}".format(sen_name,
|
||||
control_conns))
|
||||
if sen_name in self.pins:
|
||||
debug.error("Internal signal={} contained in port list. Name defined by the parent.".format(sen_name))
|
||||
return "X{}.{}".format(sram_name, sen_name)
|
||||
|
||||
def get_cell_name(self, inst_name, row, col):
|
||||
"""Gets the spice name of the target bitcell."""
|
||||
# Sanity check in case it was forgotten
|
||||
|
|
|
|||
|
|
@ -631,49 +631,3 @@ class sram_base(design, verilog, lef):
|
|||
def lvs_write(self, sp_name):
|
||||
self.sp_write(sp_name, lvs_netlist=True)
|
||||
|
||||
def get_wordline_stage_efforts(self, inp_is_rise=True):
|
||||
"""Get the all the stage efforts for each stage in the path from clk_buf to a wordline"""
|
||||
stage_effort_list = []
|
||||
|
||||
# Clk_buf originates from the control logic so only the bank is related to the wordline path
|
||||
# No loading on the wordline other than in the bank.
|
||||
external_wordline_cout = 0
|
||||
stage_effort_list += self.bank.determine_wordline_stage_efforts(external_wordline_cout, inp_is_rise)
|
||||
|
||||
return stage_effort_list
|
||||
|
||||
def get_wl_en_cin(self):
|
||||
"""Gets the capacitive load the of clock (clk_buf) for the sram"""
|
||||
# Only the wordline drivers within the bank use this signal
|
||||
return self.bank.get_wl_en_cin()
|
||||
|
||||
def get_w_en_cin(self):
|
||||
"""Gets the capacitive load the of write enable (w_en) for the sram"""
|
||||
# Only the write drivers within the bank use this signal
|
||||
return self.bank.get_w_en_cin()
|
||||
|
||||
def get_p_en_bar_cin(self):
|
||||
"""Gets the capacitive load the of precharge enable (p_en_bar) for the sram"""
|
||||
# Only the precharges within the bank use this signal
|
||||
return self.bank.get_p_en_bar_cin()
|
||||
|
||||
def get_clk_bar_cin(self):
|
||||
"""Gets the capacitive load the of clock (clk_buf_bar) for the sram"""
|
||||
# As clk_buf_bar is an output of the control logic. The cap for that module is not determined here.
|
||||
# Only the precharge cells use this signal (other than the control logic)
|
||||
return self.bank.get_clk_bar_cin()
|
||||
|
||||
def get_sen_cin(self):
|
||||
"""Gets the capacitive load the of sense amp enable for the sram"""
|
||||
# Only the sense_amps use this signal (other than the control logic)
|
||||
return self.bank.get_sen_cin()
|
||||
|
||||
def get_dff_clk_buf_cin(self):
|
||||
"""Get the relative capacitance of the clk_buf signal.
|
||||
Does not get the control logic loading but everything else"""
|
||||
total_cin = 0
|
||||
total_cin += self.row_addr_dff.get_clk_cin()
|
||||
total_cin += self.data_dff.get_clk_cin()
|
||||
if self.col_addr_size > 0:
|
||||
total_cin += self.col_addr_dff.get_clk_cin()
|
||||
return total_cin
|
||||
|
|
|
|||
Loading…
Reference in New Issue