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Removed dead code related to older characterization scheme
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@@ -190,18 +190,3 @@ class sense_amp_array(design.design):
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self.add_via_stack_center(from_layer=en_pin.layer,
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to_layer=self.en_layer,
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offset=inst.get_pin(self.amp.en_name).center())
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def input_load(self):
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return self.amp.input_load()
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def get_en_cin(self):
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"""Get the relative capacitance of all the sense amp enable connections in the array"""
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sense_amp_en_cin = self.amp.get_en_cin()
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return sense_amp_en_cin * self.word_size
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def get_drain_cin(self):
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"""Get the relative capacitance of the drain of the PMOS isolation TX"""
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from tech import parameter
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# Bitcell drain load being used to estimate PMOS drain load
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drain_load = logical_effort.convert_farad_to_relative_c(parameter['bitcell_drain_cap'])
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return drain_load
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