luke/OpenRAM
1
0
Fork 0
mirror of https://github.com/VLSIDA/OpenRAM.git synced 2026-09-03 01:23:05 +02:00
Code Issues Packages Projects Releases Wiki Activity

Removed dead code related to older characterization scheme

Browse Source
This commit is contained in:
Hunter Nichols
2020-08-27 17:30:58 -07:00
parent 42f2ff679e
commit 73b2277daa
29 changed files with 9 additions and 610 deletions
Download Patch File Download Diff File Expand all files Collapse all files
compiler/modules/replica_bitcell_array.py
-7
View File
@@ -552,13 +552,6 @@ class replica_bitcell_array(bitcell_base_array.bitcell_base_array):
bl_wire.wire_c =spice["min_tx_drain_c"] + bl_wire.wire_c # 1 access tx d/s per cell
return bl_wire
def get_wordline_cin(self):
"""Get the relative input capacitance from the wordline connections in all the bitcell"""
# A single wordline is connected to all the bitcells in a single row meaning the capacitance depends on the # of columns
bitcell_wl_cin = self.cell.get_wl_cin()
total_cin = bitcell_wl_cin * self.column_size
return total_cin
def graph_exclude_bits(self, targ_row, targ_col):
"""Excludes bits in column from being added to graph except target"""
self.bitcell_array.graph_exclude_bits(targ_row, targ_col)