Removed dead code related to older characterization scheme

compiler/modules/dummy_array.py

@@ -54,12 +54,7 @@ class dummy_array(bitcell_base_array):
                 self.connect_inst(self.get_bitcell_pins(row, col))
 
     def input_load(self):
+        # FIXME: This appears to be old code from previous characterization. Needs to be updated.
         wl_wire = self.gen_wl_wire()
         return wl_wire.return_input_cap()
-
-    def get_wordline_cin(self):
-        """Get the relative input capacitance from the wordline connections in all the bitcell"""
-        # A single wordline is connected to all the bitcells in a single row meaning the capacitance depends on the # of columns
-        bitcell_wl_cin = self.cell.get_wl_cin()
-        total_cin = bitcell_wl_cin * self.column_size
-        return total_cin
+