mirror of https://github.com/VLSIDA/OpenRAM.git
Merge branch 'master' of https://github.com/mguthaus/OpenRAM into multiport
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commit
72fc92ad95
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@ -308,7 +308,7 @@ class layout(lef.lef):
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path.path(obj=self,
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layer=layer,
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position_list=coordinates,
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width=drc["minwidth_{}".format(layer)])
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width=width)
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def add_route(self, design, layers, coordinates):
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"""Connects a routing path on given layer,coordinates,width. The
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@ -92,7 +92,8 @@ class path():
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self.add_line(layer_name=self.layer_name,
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length=abs(line_length),
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offset=offset,
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orientation="horizontal")
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orientation="horizontal",
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layer_width=self.layer_width)
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# if we have y motion
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elif pl[index][1] != pl[index + 1][1]:
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line_length = pl[index + 1][1] - pl[index][1]
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@ -104,15 +105,15 @@ class path():
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self.add_line(layer_name=self.layer_name,
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length=abs(line_length),
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offset=offset,
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orientation="vertical")
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orientation="vertical",
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layer_width=self.layer_width)
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def add_line(self, layer_name, length, offset, orientation):
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def add_line(self, layer_name, length, offset, orientation, layer_width):
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"""
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straight line object with layer_minwidth
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(orientation: "vertical" or "horizontal") default is vertical
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"""
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layer_width = drc["minwidth_{0}".format(layer_name)]
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width = layer_width
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height = length
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@ -83,7 +83,8 @@ class wire(path):
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self.add_line(layer_name=self.horiz_layer_name,
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length=abs(line_length),
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offset=temp_offset,
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orientation="horizontal")
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orientation="horizontal",
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layer_width=self.horiz_layer_width)
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elif pl[index][1] != pl[index + 1][1]:
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line_length = pl[index + 1][1] - pl[index][1]
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temp_offset = [pl[index][0] - 0.5 * self.vert_layer_width,
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@ -94,7 +95,8 @@ class wire(path):
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self.add_line(layer_name=self.vert_layer_name,
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length=abs(line_length),
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offset=temp_offset,
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orientation="vertical")
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orientation="vertical",
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layer_width=self.vert_layer_width)
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def assert_node(self, A, B):
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""" Check if the node movements are not big enough for the
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