mirror of https://github.com/VLSIDA/OpenRAM.git
Merge branch 'master' of https://github.com/mguthaus/OpenRAM into multiport
This commit is contained in:
commit
72fc92ad95
|
|
@ -308,7 +308,7 @@ class layout(lef.lef):
|
||||||
path.path(obj=self,
|
path.path(obj=self,
|
||||||
layer=layer,
|
layer=layer,
|
||||||
position_list=coordinates,
|
position_list=coordinates,
|
||||||
width=drc["minwidth_{}".format(layer)])
|
width=width)
|
||||||
|
|
||||||
def add_route(self, design, layers, coordinates):
|
def add_route(self, design, layers, coordinates):
|
||||||
"""Connects a routing path on given layer,coordinates,width. The
|
"""Connects a routing path on given layer,coordinates,width. The
|
||||||
|
|
|
||||||
|
|
@ -92,7 +92,8 @@ class path():
|
||||||
self.add_line(layer_name=self.layer_name,
|
self.add_line(layer_name=self.layer_name,
|
||||||
length=abs(line_length),
|
length=abs(line_length),
|
||||||
offset=offset,
|
offset=offset,
|
||||||
orientation="horizontal")
|
orientation="horizontal",
|
||||||
|
layer_width=self.layer_width)
|
||||||
# if we have y motion
|
# if we have y motion
|
||||||
elif pl[index][1] != pl[index + 1][1]:
|
elif pl[index][1] != pl[index + 1][1]:
|
||||||
line_length = pl[index + 1][1] - pl[index][1]
|
line_length = pl[index + 1][1] - pl[index][1]
|
||||||
|
|
@ -104,15 +105,15 @@ class path():
|
||||||
self.add_line(layer_name=self.layer_name,
|
self.add_line(layer_name=self.layer_name,
|
||||||
length=abs(line_length),
|
length=abs(line_length),
|
||||||
offset=offset,
|
offset=offset,
|
||||||
orientation="vertical")
|
orientation="vertical",
|
||||||
|
layer_width=self.layer_width)
|
||||||
|
|
||||||
def add_line(self, layer_name, length, offset, orientation):
|
def add_line(self, layer_name, length, offset, orientation, layer_width):
|
||||||
"""
|
"""
|
||||||
straight line object with layer_minwidth
|
straight line object with layer_minwidth
|
||||||
(orientation: "vertical" or "horizontal") default is vertical
|
(orientation: "vertical" or "horizontal") default is vertical
|
||||||
"""
|
"""
|
||||||
|
|
||||||
layer_width = drc["minwidth_{0}".format(layer_name)]
|
|
||||||
width = layer_width
|
width = layer_width
|
||||||
height = length
|
height = length
|
||||||
|
|
||||||
|
|
|
||||||
|
|
@ -83,7 +83,8 @@ class wire(path):
|
||||||
self.add_line(layer_name=self.horiz_layer_name,
|
self.add_line(layer_name=self.horiz_layer_name,
|
||||||
length=abs(line_length),
|
length=abs(line_length),
|
||||||
offset=temp_offset,
|
offset=temp_offset,
|
||||||
orientation="horizontal")
|
orientation="horizontal",
|
||||||
|
layer_width=self.horiz_layer_width)
|
||||||
elif pl[index][1] != pl[index + 1][1]:
|
elif pl[index][1] != pl[index + 1][1]:
|
||||||
line_length = pl[index + 1][1] - pl[index][1]
|
line_length = pl[index + 1][1] - pl[index][1]
|
||||||
temp_offset = [pl[index][0] - 0.5 * self.vert_layer_width,
|
temp_offset = [pl[index][0] - 0.5 * self.vert_layer_width,
|
||||||
|
|
@ -94,7 +95,8 @@ class wire(path):
|
||||||
self.add_line(layer_name=self.vert_layer_name,
|
self.add_line(layer_name=self.vert_layer_name,
|
||||||
length=abs(line_length),
|
length=abs(line_length),
|
||||||
offset=temp_offset,
|
offset=temp_offset,
|
||||||
orientation="vertical")
|
orientation="vertical",
|
||||||
|
layer_width=self.vert_layer_width)
|
||||||
|
|
||||||
def assert_node(self, A, B):
|
def assert_node(self, A, B):
|
||||||
""" Check if the node movements are not big enough for the
|
""" Check if the node movements are not big enough for the
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue