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fix tx binning in col mux for memories with >1 word per row

This commit is contained in:
jcirimel 2020-05-05 16:35:51 -07:00
parent 32317ce3a5
commit 71a1dd8f38
3 changed files with 6 additions and 4 deletions
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3
compiler/pgates/pgate.py
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@ -287,7 +287,8 @@ class pgate(design.design):
self.well_width = self.width + 2 * self.nwell_enclose_active self.well_width = self.width + 2 * self.nwell_enclose_active
# Height is an input parameter, so it is not recomputed. # Height is an input parameter, so it is not recomputed.
def bin_width(self, tx_type, target_width): @staticmethod
def bin_width(tx_type, target_width):
if tx_type == "nmos": if tx_type == "nmos":
bins = nmos_bins[drc("minwidth_poly")] bins = nmos_bins[drc("minwidth_poly")]

2
compiler/pgates/precharge.py
View File

@ -80,7 +80,7 @@ class precharge(design.design):
Initializes the upper and lower pmos Initializes the upper and lower pmos
""" """
if(OPTS.tech_name == "s8"): if(OPTS.tech_name == "s8"):
(self.ptx_width, self.ptx_mults) = pgate.bin_width(self, "pmos", self.ptx_width) (self.ptx_width, self.ptx_mults) = pgate.bin_width("pmos", self.ptx_width)
self.pmos = factory.create(module_type="ptx", self.pmos = factory.create(module_type="ptx",
width=self.ptx_width, width=self.ptx_width,
mults=self.ptx_mults, mults=self.ptx_mults,

3
compiler/pgates/ptx.py
View File

@ -14,7 +14,7 @@ import contact
import logical_effort import logical_effort
import os import os
from globals import OPTS from globals import OPTS
from pgate import pgate
class ptx(design.design): class ptx(design.design):
""" """
@ -109,6 +109,7 @@ class ptx(design.design):
perimeter_sd = 2 * self.poly_width + 2 * self.tx_width perimeter_sd = 2 * self.poly_width + 2 * self.tx_width
if OPTS.tech_name == "s8": if OPTS.tech_name == "s8":
# s8 technology is in microns # s8 technology is in microns
(self.width, self.mults) = pgate.bin_width(self.tx_type, self.tx_width)
main_str = "M{{0}} {{1}} {0} m={1} w={2} l={3} ".format(spice[self.tx_type], main_str = "M{{0}} {{1}} {0} m={1} w={2} l={3} ".format(spice[self.tx_type],
self.mults, self.mults,
self.tx_width, self.tx_width,